Pc Card Interface; Operation Modes; Implementing The Pcixx20 Controller As Single Cardbus Socket Device - Texas Instruments PCI7620 Implementation Manual

5 PC Card Interface

5.1 Operation Modes

There are two different modes on the PC Card interface. The first is 16-bit mode which is
analogous to the legacy ISA bus. The second is 32-bit CardBus mode which is very similar
to a PCI Bus. The terminal functions for these two modes are multiplexed and routed to the
PC Card socket. The following suggestions apply to the PC Card interface:
o Pullup resistors for the PC Card interface have been integrated into the PCIXX20
controller. These include: A14// CPERR , A15// CIRDY , A19// CBLOCK ,
A20// CSTOP , A21// CDEVSEL , A22// CTRDY , BVD2( SPKR )//CAUDIO,
CD1// CCD1, CD2 // CCD2 , INPACK // CREQ , READY// CINT , RESET// CRST ,
VS1//CVS1, VS2 //CVS2, WAIT // CSERR , and WP(IOIS16 )// CCLKRUN .
o Damping resistor on the CCLK terminal
A series-damping resistor is recommended on the CCLK signal. The damping
resistor is system dependent. If the line impedance is in the 60- to 90- Ω range, then
a 47- Ω resistor is recommended (see PC Card Standard , Revision 8).
o CD line filtering
The PCIXX20 controller features the advanced CDx line filtering circuit. It provides
90 ms of noise immunity.
o Socket power supply
For more detailed information concerning the socket power supply, please refer to
Section 3.
o Three PC Card terminals on the socket are not necessary for CardBus mode but are
necessary for 16-bit mode. These terminals are: CRSVD//D14, CRSVD//A18, and
CRSVD//D2. These terminals must be connected to the PC Card socket according to
their 16-bit designations. By default, when in CardBus mode, these terminals are
driven low. They can be placed in a high-impedance state by clearing bit 22
(CBRSVD) in the system control register at PCI configuration offset 80h.
5.2 Implementing the PCIXX20 Controller as Single CardBus Socket Controller
The PCIXX20 controller can be used as a single socket controller simply by leaving the
socket B interface unconnected. The DISABLE_SKTB bit (general control register, PCI
offset 86h, bit 4) must be set to disable function 1 (CardBus socket B). This bit can be set
via EEPROM or BIOS. Unused CardBus socket terminals must be left floating (no
connection).
PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
SCPU019
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