Omap5912 Test Modules - Texas Instruments OMAP5912 Reference Manual

Table 8.

OMAP5912 Test Modules

Module Name
ETLM
SCM
JTAG
Die ID
Production ID
Global eFuse controller
BCM
2.1 OMAP3.2 Gigacell
SPRU748A
Description
Emulation-compatible support for multiple TAP controllers.
Scan chain linking. Enables the combination of several scan chains in parallel
or serially.
The OMAP5912 1149.1 TAP controller IEEE compliant used to program the
functional test modes
A 64-bit register composed of eFuse cells programmed during fabrication
process. Each die ID is unique, as it is created from the wafer, lot, and factory
numbers, plus the die x/y coordinates in the wafer.
An additional 64-bit register of eFuse cells used to include specific OMAP5912
needs. One R&D eFuse to distinguish the OMAP5912 production version from
the prototype version.
OMAP3.2 gigacell eFuse controller. This eFuse controller is closely coupled
with the gigacell. It is mainly used to control its internal dedicated eFuses for
memory repair and enables access to the die ID registers.
BIST combiner module. Manages OMAP5912 BIST controller from the MPU or
TAP controller
The OMAP 3.2 gigacell used by OMAP5912 is called OMAP 3.2.
This gigacell features:
-
ARM926EJ core including:
J
ARM926EJS, supporting multiple operating systems (Symbian,
Linux, WinCE, and others)
J
MMU with translation lookaside buffer (TLB)
J
L1 16K-byte, four-way set-associative instruction cache
J
L1 8K-byte, four-way set-associative data cache with write buffer
-
MPU level 1 interrupt handler
-
Embedded trace macrocell module, ETM version 2.a in 13-bit mode
configuration or in 17-bit demultiplexed mode configuration
OMAP5912 Description
Introduction 25