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Overview
Figure 1.
Top-Level OMAP5912
OMAP5912
CompactFlash
Boot ROM
Secure eFUSE
Secure RAM
Security layer
Flash
E
16
M
and
I
SRAM
F
S
E
M
16
Memory interface
SDRAM
I
traffic controller (TC)
F
F
O
O
O
C
C
C
P
P
P
−
−
−
T1
T2
I
Frame
Buffer
Switch
GDD
VLYNQ
SSI
JTAG/emulation I/F
14
Introduction
TMS320C55x DSP
(Instruction cache, SARAM,
Endianism
32
DARAM, DMA,
conversion
H/W accelerators)
DSP
Endianism
MMU
conversion
16
32
32
MPU
interface
32
32
MPU bus
32
System
DMA
controller
MPU core
ARM926EJS
32
(Instruction
cache, data
cache, MMU)
LCD
I/F
OSC
ETM9
16
12 MHz
The OMAP5912 includes the microprocessor unit (MPU) subsystem, the
digital signal processor (DSP) subsystem, the system direct memory access
(SDMA), and part of the L3 and L4 interconnects. All other components of
OMAP5912 are associated with the OMAP gigacell revision 3.2.
The OMAP5912 device provides a secure environment to run secure
applications. The security hardware components include:
-
OMAP3.2 gigacell security state machine
-
Dedicated secure RAM
-
Secure boot ROM
-
Secure electrical fuse (eFuse) components
-
Secure peripherals
DSP
DSP private peripherals
public peripheral bus
Timers (3)
16
Watchdog timer
Level 1/2 interrupt handlers
DSP public (shared)
peripheral bus
16
MPU public
peripheral bus
32
MPU
peripheral
bridge
32
MPU private peripherals
Timers (3)
Watchdog timer
32
MPU private
Level 1/2 interrupt handlers
peripheral bus
Configuration registers
System DMA
Secure watchdog
ULPD
DES/3DES
Clock and reset management
SHA1/MD5
32-kHz watchdog
OSC
LCDCONV
Clock
Reset
External clock
32 kHz
requests
DSP public peripherals
McBSP1 (audio PCM I/F)
McBSP3 (optical I/F)
MCSI1 (Bluetooth voice I/F)
MCSI2 (moden voice)
MPU/DSP shared peripherals
Mailbox
MPU/DSP static shared
8 x GPTIMERS
SPI
UART1, 2, 3
2
I
C
MMCSDIO2
McBSP2
MPU/DSP dynamic shared
GPIO1, 2, 3, 4
32-kHz synchro counter
MPU public peripherals
USB controllers
SoSSI
32
CCP
µWire I/F
Camera I/F
RTC
PWT
PWL
Keyboard I/F
HDQ/1-Wire
MMCSDIO1
MPUIO
RNG
LPG1, 2
FAC
OS timer
SPRU748A
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