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RM0453
35.8.12
USART receive data register (USART_RDR)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 RDR[8:0]: Receive data value
35.8.13
USART transmit data register (USART_TDR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Note: This register must be written only when TXE/TXFNF = 1.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
Figure
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Contains the data character to be transmitted.
The USART_TDR register provides the parallel interface between the internal bus and the
output shift register (see
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
24
23
22
Res.
Res.
Res.
8
7
6
r
r
r
305).
24
23
22
Res.
Res.
Res.
8
7
6
rw
rw
rw
Figure
305).
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RDR[8:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TDR[8:0]
rw
rw
rw
rw
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
rw
rw
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