Figure 333. Lpuart Block Diagram - ST STM32WL55JC Reference Manual

RM0453
the data in the FIFO, but also the error flags associated to each character (Parity error,
Noise error and Framing error flags).
Note: The received data is stored in the RXFIFO together with the corresponding flags. However,
only the data are read when reading the RDR.
The status flags are available in the LPUART_ISR register.
It is possible to define the TXFIFO and RXFIFO levels at which the Tx and RX interrupts are
triggered. These thresholds are programmed through RXFTCFG and TXFTCFG bitfields in
LPUART_CR3 control register.
In this case:
•
The RXFT flag is set in the LPUART_ISR register and the corresponding interrupt (if
enabled) is generated, when the number of received data in the RXFIFO reaches the
threshold programmed in the RXFTCFG bits fields.
This means that the RXFIFO is filled until the number of data in the RXFIFO is equal to
the programmed threshold.
RXFTCFG data have been received: one data in LPUART_RDR and (RXFTCFG - 1)
data in the RXFIFO. As an example, when the RXFTCFG is programmed to '101', the
RXFT flag is set when a number of data corresponding to the FIFO size has been
received: FIFO size - 1 data in the RXFIFO and 1 data in the LPUART_RDR. As a
result, the next received data does not set the overrun flag.
•
The TXFT flag is set in the LPUART_ISR register and the corresponding interrupt (if
enabled) is generated when the number of empty locations in the TXFIFO reaches the
threshold programmed in the TXFTCFG bits fields.
This means that the TXFIFO is emptied until the number of empty locations in the
TXFIFO is equal to the programmed threshold.
36.4.5 LPUART transmitter
The transmitter can send data words of either 7 or 8 or 9 bits, depending on the M bit status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin.
Character transmission
During an LPUART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see
When FIFO mode is enabled, the data written to the LPUART_TDR register are queued in
the TXFIFO.
Every character is preceded by a start bit which corresponds to a low logic level for one bit
period. The character is terminated by a configurable number of stop bits.
The number of stop bits can be 1 or 2.
Note: The TE bit must be set before writing the data to be transmitted to the LPUART_TDR.
The TE bit should not be reset during data transmission. Resetting the TE bit during the
transmission corrupts the data on the TX pin as the baud rate counters is frozen. The
current data being transmitted are lost.
An idle frame is sent after the TE bit is enabled.
Low-power universal asynchronous receiver transmitter (LPUART)
RM0453 Rev 2
Figure 332).
1211/1454
1257