STMicroelectronics RM0365 Reference Manual page 1077

Revision history
Date
10-Oct-2016
1077/1080
Table 196. Document revision history (continued)
Revision
Updated COMP section:
– Updated
combined in a window comparator for STM32F302xB/C only.
– Updated
– Updated
(COMP2_CSR)
STM32F302x6/8/D/E devices' and updating bit 9 description.
Updated FMC section:
– Updated
asynchronous transactions
– Updated
(FMC_SR2..4)
– Updated
1..4 (FMC_BTR1..4)
– Updated
(FMC_BWTR1..4)
6 – Updated
(continued) common memory access
adding note 2.
– Updated
– Updated
(FMC_PMEM2..4)
– Updated
(FMC_PATT2..4)
– Updated
Updated ADC section:
– Updated
Dual ADC modes (STM32F302xB/C/D/E only)
'STM32F302xB/xC only' by 'STM32F302xB/C/D/E only'.
– Updated
b) and removing 'or 10'.
Updated SPI2S section:
Updated Figure 357: I2S full-duplex block
I2S full duplex.
DocID025202 Rev 7
Changes
Section 17.2: COMP main features
Figure 118: Comparator 1 and 2 block
Section 17.5.2: COMP2 control and status register
replacing note 2 on bit 9 by 'not available in
Section 14.5.4: NOR Flash/PSRAM controller
putting 'de-asserting the NOE signal'.
Section : FIFO status and interrupt register 2..4
bit0 (IRS) and Bit2 (IFS) adding a note.
Section : SRAM/NOR-Flash chip-select timing registers
adding new paragraph.
Section : SRAM/NOR-Flash write timing registers 1..4
adding new paragraph.
Figure 49: NAND Flash/PC Card controller waveforms for
replacing 'MEMxHIZ' by 'MEMxHIZ+1' and
Section 14.6.5: NAND Flash prewait
Common memory space timing register 2..4
MEMHOLD[7:0] description.
Attribute memory space timing registers 2..4
ATTHOLD[7:0] description.
Section 14.3: AHB interface.
Section 15.2: ADC main features
Section 15.3.3: Clocks note, replacing option a) by option
RM0365
COMP1 and COMP2
diagrams.
functionality.
and Section 15.3.29:
replacing
diagram. in Section 30.7.2: