STMicroelectronics RM0365 Reference Manual page 1075

Revision history
Date
10-Oct-2016
1075/1080
Table 196. Document revision history (continued)
Revision
Updated TIMER section:
– Updated Section Table 115.: TIM1 internal trigger connection
removing the line where the "Slave TIM" is mentioned as reserved.
– Updated Section 22.4.18: Slave mode: Combined reset + trigger
mode (TIM15 only)
– Updated Section 22.5.7: TIM15 capture/compare mode register 1
(TIM15_CCMR1)
replacing bit 7 'reserved' by OC1CE.
– Updated Section 21.4.11: TIMx prescaler
Section 23.4.7: TIM6 prescaler (TIMx_PSC)
description
– Updated Section 20.4.5: TIM1 status register (TIMx_SR)
Section 20.4.25: TIM1 register map
– Added Section 20.3.4: External trigger
– Updated Section 20.3.27: DMA burst mode
registers can be written with a null value'.
– Updated Section 20.3.28: Debug mode
paragraph.
– Updated Table 116: Output control bits for complementary OCx and
OCxN channels with break feature
timers (TIM1).
Updated RCC section:
– Updated Figure 14: STM32F302x6/8 clock tree
6
'USARTx(x=1,2,3)' by 'USART1'.
– Updated Figure 13: STM32F302xD/E clock tree
going to TIM2/3/4 when PLLCLK is timer clock source.
– Updated Section 9.4.2: Clock configuration register (RCC_CFGR)
renaming USBPRES by USBPRE and adding bit22 USBPRE
description.
– Updated Section 9.4.9: RTC domain control register (RCC_BDCR)
LSEDRV[1:0] bits: '01' and '10' combinations swapped.
– Updated Section 9.2.9: RTC clock
and functional under system reset" when the RTC clock is LSE.
Updated Embedded Flash memory section:
– Updated Section 4.5.1: Flash access control register (FLASH_ACR)
bits LATENCY[2:0] replacing SYSCLK by HCLK.
Updated operational amplifier section (OPAMP) section:
– Updated Table 105: Connections with dedicated
Updated DEBUG section:
– Updated Section 33.14.2: Debug support for timers, watchdog,
bxCAN and I2C
outputs.
– Updated Section 33.14.4: Debug MCU APB1 freeze register
(DBGMCU_APB1_FZ)
freeze register (DBGMCU_APB2_FZ)
description.
DocID025202 Rev 7
Changes
adding (TIM15 only) on the title.
and Section 22.5.18: TIM15 register map
CC5IF and CC6IF bit names.
input.
adding 'for safety purposes'
in Section 20: Advanced-control
adding "the RTC remains clocked
adding paragraphs for timers having complementary
and Section 33.14.5: Debug MCU APB2
DBG_TIMx_STOP bit
RM0365
(TIMx_PSC),
PSC[15:0] bits
and
adding note 'reserved
replacing
adding x2 factor
I/O.