STMicroelectronics RM0365 Reference Manual page 1076

RM0365
Date
10-Oct-2016
Table 196. Document revision history (continued)
Revision
Updated RTC section:
– Updated
RTC_TAMP3 and replacing RTC_WUTR 'ck_apre' input by 'ck_spre'
input.
– Updated
configuration register (RTC_TAFCR)
bits and adding note on the Tamper 3 bits.
– Updated WUCKSEL bits in
– Added case of RTC clocked by LSE in
RTC.
– Added caution at the end of
(RTC_CR).
– Updated caution at the end of
alternate function configuration register
– Updated ADD1H and SUB1H bit descriptions in
control register
– Updated
backup registers
reset when the Flash readout protection is disabled.
Updated Touch sensing controller section:
– Updated
adding note about the TSC control register configuration forbidden.
6 – Updated
(continued) for CTPL[3:0] bits and PGPSC[2:0] bits.
Updated USART section:
– Updated
replacing 'USART4, 5' by 'UART4, 5'.
– Updated
adding paragraph "determining the maximum USART baudrate".
– Updated whole USART document replacing any occurrence of:
nCTS by CTS, nRTS by RTS, SCLK by CK.
– Updated
replacing "w" by "rc_wl".
– Updated
RTOF field replacing USART_CR2 by USART_CR1.
– Updated
bit 11 description adding a note.
– Updated
transmitter
USART_regname.
– Changed tWUSTOP to tWUUSART and updated
Tolerance of the USART receiver to clock
– Updated
RWU bit available independently of the wakeup from stop feature
availability.
– Updated
DocID025202 Rev 7
Changes
Figure 283: RTC block diagram
Section 27.6.16: RTC tamper and alternate function
Figure 283: RTC block
Section 27.6.3: RTC control register
Section 27.6.16: RTC tamper and
(RTC_CR).
Section : RTC backup registers
(RTC_BKPxR): RTC_BKPxR registers cannot be
Section 19.3.4: Charge transfer acquisition sequence
Section 19.6.1: TSC control register (TSC_CR)
Section Table 152.: STM32F302xx USART features
Section 29.5.17: Wakeup from Stop mode using USART
Section 29.8.9: Interrupt flag clear register (USART_ICR)
Section 29.8.8: Interrupt and status register (USART_ISR)
Section 29.8.3: Control register 3 (USART_CR3)
Section 29: Universal synchronous asynchronous receiver
(USART)changing register name USARTx_regname in
Section 29.8.8: Interrupt and status register (USART_ISR)
Section 29.8.12: USART register map
Revision history
adding note on
adding Tamper 2, Tamper 3
diagram.
Section 27.3.9: Resetting the
(RTC_TAFCR).
Section 27.6.3: RTC
and Section 27.6.19: RTC
adding note
'ONEBIT'
Section 29.5.5:
deviation.
RWU bit.
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