STMicroelectronics RM0365 Reference Manual page 1078

RM0365
Date
10-Oct-2016
Table 196. Document revision history (continued)
Revision
Updated interrupts and events section:
– Updated
mapping
updating the note and adding STM32F302xB/C/D/E only in EXTI
lines 26, 28.
– Updated
register (EXTI_EMR1)
– Updated
trigger selection register
register (EXTI_SWIER1)
up to 29, 31 reserved.
– Updated
Section 13.3.8: Event mask register (EXTI_EMR2)
– Updated
(EXTI_RTSR2),
(EXTI_FTSR2),
(EXTI_SWIER2)
6
bit 0 reserved.
(continued)
Updated DMA section:
– updated
(when bits PINC = MINC =
Updated I2C2 section:
– Updated
– Updated
in Section : I2C
– Updated
SCLDEL[3:0] and SDADEL[3:0] bits description.
– Updated
master mode
adding the sentence "The STM32CubeMX tool calculates and
provides the I2C_TIMIGR content in the I2C configuration window".
– Updated
communication initialization (address phase) paragraph.
– Updated
the note of bit 13 'START' description.
DocID025202 Rev 7
Changes
Section 13.2.6: External and internal interrupt/event line
removing STM32F302x6/8 in EXTI lines 21, 34 and 35,
Interrupt mask register (EXTI_IMR1)
bits 29, 31 reserved.
Rising trigger selection register
(EXTI_FTSR1),
and Pending register (EXTI_PR1)
Section 13.3.7: Interrupt mask register (EXTI_IMR2)
Section 13.3.9: Rising trigger selection register
Section 13.3.10: Falling trigger selection register
Section 13.3.11: Software interrupt event register
and Section 13.3.12: Pending register (EXTI_PR2)
Table 34: Programmable data width & endian behavior
1).
Figure 286: Setup and hold
Section 28.4.4: I2C initialization
timings.
Section 28.7.5: Timing register (I2C_TIMINGR)
Section 28.4.4: I2C initialization,
and Section 28.7.5: Timing register (I2C_TIMINGR)
Section 28.4.8: I2C master mode
Section 28.7.2: Control register 2 (I2C_CR2)
Revision history
and Event mask
(EXTI_RTSR1), Falling
Software interrupt event
bits 23
bit 1 reserved.
timings.
updating and adding notes
Section 28.4.8: I2C
note in Master
completing
1078/1080
and
1079