STMicroelectronics RM0365 Reference Manual page 1074

RM0365
Date
22-Jan-2015
22-Sep-2015
Table 196. Document revision history (continued)
Revision
Interrupts and events
– Table: STM32F302xB/C/D/E vector table
Analog to digital converter (ADC)
– Section: ADC main features
Digital to analog converter (DAC)
– Section: DAC1 main features
– Figure: DAC1 block diagram: updated the related note.
Comparator (COMP)
– Section: COMP main features
– Section: COMP registers
Operational amplifier (OPAMP)
– Section OPAMP main features
4
– Section: OPAMP registers
(continued)
Advanced-control timers (TIM1)
– Section: TIM1/TIM8 introduction
General-purpose timers (TIM2/TIM3/TIM4)
– Section: TIM2/TIM3/TIM4/TIM5 introduction
Inter-integrated circuit (I2C) interface
– Section: I2C implementation
Serial peripheral interface / inter-IC sound (SPI/I2S)
– Section: SPI implementation
Universal synchronous asynchronous receiver transmitter
(USART)
– Section: USB implementation
Debug support (DBG)
– Section: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
System and memory overview
– Updated
Flexible static memory controller (FSMC)
– Renamed FMC as FSMC in the section title and introduction.
Digital-to-analog converter (DAC1)
– updated
Reset and clock control (RCC)
5
– Section 10.4.13: Clock configuration register 3
added a note to USART2SW and USART3SW bit descriptions
– Section 10.4.10: Control/status register
[31:25] and bit 23
Universal synchronous asynchronous receiver transmitter
(USART)
– Updated the configuration for USART5 in
USART features
DocID025202 Rev 7
Changes
Figure 3: STM32F302xD/E system
Section 16.5.3: DAC output
Revision history
architecture,
voltage.
(RCC_CFGR3):
(RCC_CSR): updated bits
Table 152: STM32F302xx
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