Hitachi SH7751 Hardware Manual page 53

Table 1.2 Pin Functions (cont)
No. Pin Name I/O
26 D8 I/O
27 D9 I/O
28 D10 I/O
29 VDDQ Power IO VDD
30 VSSQ Power IO GND
31 D11 I/O
32 D12 I/O
33 D13 I/O
34 D14 I/O
35 D15 I/O


36 / O
DQM0


37 / O
DQM1
38 RD/ O
39 CKIO O
40 Reserved
41 VDDQ Power IO VDD
42 VSSQ Power IO GND
43 Reserved


44 / / O
 
45 CKE O

46 O
47 VDD Power Internal VDD
48 VSS Power Internal GND


49 O


50 O
51 A0 O
52 A1 O
53 A2 O
54 A3 O
55 VDDQ Power IO VDD
Rev. 3.0, 04/02, page 14 of 1064
Function Reset
Data
Data
Data
Data
Data
Data
Data
Data
D7–D0
select signal
D15–D8
select signal
Read/write
Clock output
Do not connect
Do not connect


Read/ /
 
Clock output
enable

Chip select 2
Chip select 3
Address
Address
Address
Address
Memory Interface
SRAM DRAM




RD/





( )



( )
SDRAM PCMCIA MPX
DQM0
DQM1
RD/
CKIO

 
CKE





A8
A9
A10
A11
A12
A13
A14
A15
RD/