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31
R0 _ BANK0*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R8
R9
R10
R11
R12
R13
R14
R15
SR
GBR
MACH
MACL
PR
PC
(a) Register configuration
in user mode
Notes: *1 The R0 register is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
*2 Banked registers
*3 Banked registers
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
*4 Banked registers
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processor Mode
Rev. 3.0, 04/02, page 38 of 1064
0
31
1,
2
*
2
2
2
2
2
2
2
(b) Register configuration in
privileged mode (RB = 1)
0
R0 _ BANK1*
1,
3
*
R1 _ BANK1*
3
R2 _ BANK1*
3
R3 _ BANK1*
3
R4 _ BANK1*
3
R5 _ BANK1*
3
R6 _ BANK1*
3
R7 _ BANK1*
3
R8
R9
R10
R11
R12
R13
R14
R15
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
SGR
DBR
R0 _ BANK0*
1,
4
*
R1 _ BANK0*
4
R2 _ BANK0*
4
R3 _ BANK0*
4
R4 _ BANK0*
4
R5 _ BANK0*
4
R6 _ BANK0*
4
R7 _ BANK0*
4
31
R0 _ BANK0*
1,
4
*
R1 _ BANK0*
4
R2 _ BANK0*
4
R3 _ BANK0*
4
R4 _ BANK0*
4
R5 _ BANK0*
4
R6 _ BANK0*
4
R7 _ BANK0*
4
R8
R9
R10
R11
R12
R13
R14
R15
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
SGR
DBR
R0 _ BANK1*
1,
3
*
R1 _ BANK1*
3
R2 _ BANK1*
3
R3 _ BANK1*
3
R4 _ BANK1*
3
R5 _ BANK1*
3
R6 _ BANK1*
3
R7 _ BANK1*
3
(c) Register configuration in
privileged mode (RB = 0)
0
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