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14.2.5
DMA Operation Register (DMAOR)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
The COD bit can be written to in the SH7750S only.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. When the
DDT bit is set to 1, CPU writes to SAR0, DAR0, DMATCR0, and CHCR0 are masked.
Bit 15: DDT
0
1
Note: %$9/ (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the %$9/ pin function is enabled and this pin becomes an active-low output.
Rev. 4.0, 04/00, page 436 of 850
31
30
—
—
0
0
R
R
23
22
—
—
0
0
R
R
15
14
DDT
—
0
0
R/W
R
7
6
—
—
0
0
R
R
Description
Normal DMA mode
On-demand data transfer mode
29
28
—
—
0
0
R
R
21
20
—
—
0
0
R
R
13
12
—
—
0
0
R
R
5
4
—
COD
0
0
R
R/(W)
27
26
—
—
0
0
R
R
19
18
—
—
0
0
R
R
11
10
—
—
PR1
0
0
R
R
R/W
3
2
—
AE
NMIF
0
0
R
R/(W)
R/(W)
25
24
—
—
0
0
R
R
17
16
—
—
0
0
R
R
9
8
PR0
0
0
R/W
1
0
DME
0
0
R/W
(Initial value)
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