Hitachi SH7751 Hardware Manual page 31

Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle:
Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ...................... 981
Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle:
Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)........................ 982
Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Burst (RCD [1:0] = 01, TRWL [2:0] = 010).................................................... 983
Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010).... 984
Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command,
Burst (TRWL [2:0] = 010)............................................................................... 985
Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) ..... 986
Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001) 987
Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001).................. 988
Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)................... 989
Figure 23.34(b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)...................... 990
Figure 23.35 DRAM Bus Cycles
(1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001
(2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 ................................. 991
Figure 23.36 DRAM Bus Cycle
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)................ 992
Figure 23.37 DRAM Bus Cycle
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)................ 993
Figure 23.38 DRAM Burst Bus Cycle
(EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001)................ 994
Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)...................................... 995
Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000)............................................ 996
Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000)............................................ 997
Figure 23.42 DRAM Burst Bus Cycle
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ........ 998
Figure 23.43 DRAM Burst Bus Cycle
(Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) ........ 999
Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)...................................... 1000
Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)..................................... 1001
Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)..................................... 1002
Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 000, TRC [2:0] = 001) ............................................................. 1003
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