Hitachi SH7751 Hardware Manual page 62

Table 1.2 Pin Functions (cont)
No. Pin Name I/O
247 VDDQ Power IO VDD
248 VSSQ Power IO GND
249 VDD-PLL2 Power PLL2 VDD
250 VSS-PLL2 Power PLL2 GND
251 VDD-PLL1 Power PLL1 VDD
252 VSS-PLL1 Power PLL1 GND
253 VDD-CPG Power CPG VDD
254 VSS-CPG Power CPG GND
255 XTAL O
256 EXTAL I
I: Input
O: Output
I/O: Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby
mode, supply power to RTC as a minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix
D.
* I/O attribute is I/O when used as a port.
Function Reset
Crystal
resonator
External input
clock/crystal
resonator
Memory Interface
SRAM DRAM
Rev. 3.0, 04/02, page 23 of 1064
SDRAM PCMCIA MPX