Figure 2.3 General Registers - Hitachi SH7751 Hardware Manual

SR.MD = 0 or
(SR.MD = 1, SR.RB = 0)
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
Programming Note: As the user's R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an
exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the
interrupt handler to save and restore the user's R0–R7 (R0_BANK0–R7_BANK0).
After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are
undefined.
Rev. 3.0, 04/02, page 40 of 1064
R0
R0_BANK0
R1
R1_BANK0
R2
R2_BANK0
R3
R3_BANK0
R4
R4_BANK0
R5
R5_BANK0
R6
R6_BANK0
R7
R7_BANK0
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R8
R8
R9
R9
R10
R10
R11
R11
R12
R12
R13
R13
R14
R14
R15
R15

Figure 2.3 General Registers

(SR.MD = 1, SR.RB = 1)
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15