Hitachi SH7751 Hardware Manual page 29

Figure 17.7 Sample Initialization Flowchart ....................................................................... 695
Figure 17.8 Sample Transmission Processing Flowchart.................................................... 697
Figure 17.9 Sample Reception Processing Flowchart ......................................................... 699
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode...................................... 701
Figure 17.11 Retransfer Operation in SCI Receive Mode..................................................... 702
Figure 17.12 Retransfer Operation in SCI Transmit Mode ................................................... 703
Figure 17.13 Procedure for Stopping and Restarting the Clock............................................ 704
Figure 18.1 16-Bit Port A.................................................................................................... 708
Figure 18.2 16-Bit Port B.................................................................................................... 709
Figure 18.3 SCK Pin ........................................................................................................... 710
Figure 18.4 TxD Pin............................................................................................................ 711
Figure 18.5 RxD Pin............................................................................................................ 711
Figure 18.6 MD1/TxD2 Pin ................................................................................................ 712
Figure 18.7 MD2/RxD2 Pin ................................................................................................ 712
Figure 18.8 MD0/SCK2 Pin................................................................................................ 713
Figure 18.9 MD7/CTS2 Pin ................................................................................................ 714
Figure 18.10 MD8/RTS2 Pin ................................................................................................ 715
Figure 19.1 Block Diagram of INTC .................................................................................. 730
Figure 19.2 Example of IRL Interrupt Connection ............................................................. 733
Figure 19.3 Interrupt Operation Flowchart ......................................................................... 748
Figure 20.1 Block Diagram of User Break Controller ........................................................ 752
Figure 20.2 User Break Debug Support Function Flowchart .............................................. 772
Figure 21.1 Block Diagram of H-UDI Circuit .................................................................... 778
Figure 21.2 TAP Control State Transition Diagram............................................................ 798
Figure 21.3 H-UDI Reset .................................................................................................... 799
Figure 22.1 PCIC Block Diagram ....................................................................................... 803
Figure 22.2 PIO Memory Space Access.............................................................................. 887
Figure 22.3 PIO I/O Space Access ...................................................................................... 888
Figure 22.4 Local Address Space Accessing Method ......................................................... 889
Figure 22.5 Example of DMA Transfer Control Register Settings ..................................... 893
Figure 22.6 Example of DMA Transfer Flowchart ............................................................. 895
Figure 22.7 Master Write Cycle in Host Mode (Single) ..................................................... 899
Figure 22.8 Master Read Cycle in Host Mode (Single) ...................................................... 900
Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) ................................ 901
Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) ................................. 902
Figure 22.11 Target Read Cycle in Non-Host Mode (Single)............................................... 904
Figure 22.12 Target Write Cycle in Non-Host Mode (Single).............................................. 905
Figure 22.13 Target Memory Read Cycle in Host Mode (Burst).......................................... 906
Figure 22.14 Target Memory Write Cycle in Host Mode (Burst) ......................................... 907
Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping) ............... 908
Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping)................. 909
Figure 22.17 Endian Conversion Modes for Peripheral Bus................................................. 910
Figure 22.18 Peripheral Bus
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PCI Bus Data Alignment.................................................... 911