Hitachi SH7751 Hardware Manual page 35

Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) ........................... 285
Table 12.1 TMU Pins ........................................................................................................... 288
Table 12.2 TMU Registers ................................................................................................... 289
Table 12.3 TMU Interrupt Sources ...................................................................................... 303
Table 13.1 BSC Pins ............................................................................................................ 308
Table 13.2 BSC Registers .................................................................................................... 310
Table 13.3 External Memory Space Map............................................................................. 312
Table 13.4 PCMCIA Interface Features............................................................................... 314
Table 13.5 PCMCIA Support Interfaces .............................................................................. 315
Table 13.6 Idle Insertion between Accesses......................................................................... 333
Table 13.7 When MPX Interface is Set (Areas 0 to 6)......................................................... 341
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment ...................... 360
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment ...................... 361
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ........................ 362
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment ................... 363
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment ................... 364
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment ..................... 365
Table 13.14 Relationship between AMXEXT and AMX2-0 Bits and Address Multiplexing 379
Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM
Address Pins (32-Bit Bus Width, AMX2-AMX0 = 000, AMXEXT = 0) ......... 395
Table 13.16 Cycles in Which Pipelined Access Can Be Used ............................................... 409
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface .......... 424
Table 14.1 DMAC Pins ........................................................................................................ 467
Table 14.2 DMAC Pins in DDT Mode ................................................................................ 468
Table 14.3 DMAC Registers ................................................................................................ 468
Table 14.4 Selecting External Request Mode with RS Bits ................................................. 487
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits .................. 489
Table 14.6 Supported DMA Transfers ................................................................................. 493
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ..... 499
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode ............. 500
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ................. 501
Table 14.10 Conditions for Transfer between External Memory and an External Device
with DACK, and Corresponding Register Settings ............................................ 519
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode......................................... 524
Table 14.12 DMAC Pins ........................................................................................................ 551
Table 14.13 DMAC Pins in DDT Mode ................................................................................ 552
Table 14.14 Register Configuration ....................................................................................... 553
Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)................................... 560
Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode........................ 563
Table 14.17 Function of
Table 14.18 DTR Format for Clearing Request Queues ........................................................ 564
Table 14.19 DMAC Interrupt-Request Codes........................................................................ 565
Table 15.1 SCI Pins.............................................................................................................. 572
Rev. 3.0, 04/02, page xxxiv of xxxviii

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