Hitachi SH7751 Hardware Manual page 64

Table 1.3 Pin Functions (cont)
Pin
No. Number Pin Name
28 J3 D10
29 K3 VDDQ
30 L3 VSSQ
31 J2 D11
32 J1 D12
33 K4 D13
34 K2 D14
35 K1 D15


36 L2 /
DQM0


37 M4 /
DQM1
38 M3 RD/
39 M1 CKIO
40 M2 NC
41 P3 VDDQ
42 L1 VSSQ
43 N3 NC

44 P1 /


/
 
45 N2 CKE

46 N1
47 P4 VDD
48 R4 VSS


49 N4


50 R3
51 R1 A0
52 T4 A1
53 T3 A2
54 T2 A3
55 P2 VDDQ
I/O Function
I/O Data
Power IO VDD
Power IO GND
I/O Data
I/O Data
I/O Data
I/O Data
I/O Data
O D7–D0
select signal
O D15–D8
select signal
O Read/write
O Clock output
Do not connect
Power IO VDD
Power IO GND
Do not connect


O Read/ /
 
O Clock output
enable

O
Power Internal VDD
Power Internal GND
O Chip select 2
O Chip select 3
O Address
O Address
O Address
O Address
Power IO VDD
Reset SRAM DRAM




RD/





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Rev. 3.0, 04/02, page 25 of 1064
Memory Interface
SDRAM PCMCIA
DQM0
DQM1
RD/
CKIO

 
CKE



)


)
MPX
A10
A11
A12
A13
A14
A15
RD/