Data Cache - Motorola MC68030 User Manual

On-Chip Cache Memories
instruction word and loads the cache entry, provided the entry is cachable. A burst mode
operation may be requested to fill an entire cache line. If the function code and address bits
match and the corresponding long word is not valid (but one or more of the other three valid
bits for that line are set) a single entry fill operation replaces the required long word only,
using a normal prefetch bus cycle or cycles (no burst).

6.1.2 Data Cache

The data cache stores data references to any address space except CPU space (FC=$7),
including those references made with PC relative addressing modes and accesses made
with the MOVES instruction. Operation of the data cache is similar to that of the instruction
cache, except for the address comparison and cache filling operations. The tag of each line
in the data cache contains function code bits FC0, FC1, and FC2 in addition to address bits
A31–A8. The cache control circuitry selects the tag using bits A7–A4 and compares it to the
corresponding bits of the access address to determine if a tag match has occurred. Address
bits A3–A2 select the valid bit for the appropriate long word in the cache to determine if an
entry hit has occurred. Misaligned data transfers may span two data cache entries. In this
case, the processor checks for a hit one entry at a time. Therefore, it is possible that a
portion of the access results in a hit and a portion results in a miss. The hit and miss are
treated independently. Figure 6-3 illustrates the organization of the data cache.
The operation of the data cache differs for read and write cycles. A data read cycle operates
exactly like an instruction cache read cycle; when a miss occurs, an external cycle is initiated
to obtain the operand from memory, and the data is loaded into the cache if the access is
cachable. In the case of a misaligned operand that spans two cache entries, two long words
are required from memory. Burst mode operation may also be initiated to fill an entire line of
the data cache. Read accesses from the CPU address space and address translation table
search accesses are not stored in the data cache.
The data cache on the MC68030 is a writethrough cache. When a hit occurs on a write cycle,
the data is written both to the cache and to external memory (provided the MMU validates
the access), regardless of the operand size and even if the cache is frozen. If the MMU
determines that the access is invalid, the write is aborted, the corresponding entry is
invalidated, and a bus error exception is taken. Since the write to the cache completes
before the write to external memory, the cache contains the new value even if the external
write terminates in a bus error. The value in the data cache might be used by another
instruction before the external write cycle has completed, although this should not have any
adverse consequences. Refer to 7.6 Bus Synchronization for the details of bus
synchronization.
6-6 MC68030 USER'S MANUAL MOTOROLA