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The data cache provides buffers for load and store bus operations. All the data for the
corresponding address queues (load and store data queues) is located in the data cache. The
data queues are considered temporary storage for the cache and not part of the BIU. The
data cache also provides storage for the cache tags required for memory coherency and
performs the cache block replacement PLRU function.
The data cache supplies data to the GPRs and FPRs by means of the load/store unit. The
MPC750's LSU is directly coupled to the data cache to allow efficient movement of data to
and from the general-purpose and floating-point registers. The load/store unit provides all
logic required to calculate effective addresses, handles data alignment to and from the data
cache, and provides sequencing for load and store string and multiple operations. Write
operations to the data cache can be performed on a byte, half-word, word, or double-word
basis.
The instruction cache provides a 128-bit interface to the instruction unit, so four
instructions can be made available to the instruction unit in a single clock cycle. The
instruction unit accesses the instruction cache frequently in order to sustain the high
throughput provided by the six-entry instruction queue.
3.1 Data Cache Organization
The data cache is organized as 128 sets of eight blocks as shown in Figure 3-2. Each block
consists of 32 bytes, two state bits, and an address tag. Note that in the PowerPC
architecture, the term 'cache block,' or simply 'block,' when used in the context of cache
implementations, refers to the unit of memory at which coherency is maintained. For the
MPC750, this is the eight-word cache line. This value may be different for other PowerPC
implementations.
Each cache block contains eight contiguous words from memory that are loaded from an
eight-word boundary (that is, bits A[27 - 31] ofthe logical (effective) addresses are zero); as
a result, cache blocks are aligned with page boundaries. Note that address bits A[20-26]
provide the index to select a cache set. Bits A[27-31] select a byte within a block. The two
state bits implement a three-state MEl (modified/exclusive/invalid) protocol, a coherent
subset of the standard four-state MESI (modified/exclusive/shared/invalid) protocol. The
MEl protocol is described in Section 3.3.2, "MEl Protocol." The tags consist of bits
PA [0-19] . Address translation occurs in parallel with set selection (from A[20-26]), and the
higher-order address bits (the tag bits in the cache) are physical.
The MPC750's on-chip data cache tags are single-ported, and load or store operations must
be arbitrated with snoop accesses to the data cache tags. Load or store operations can be
performed to the cache on the clock cycle immediately following a snoop access if the
snoop misses; snoop hits may block the data cache for two or more cycles, depending on
whether a copy-back to main memory is required.
Chapter
3. L 1 Instruction and Data Cache Operation
3-3
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