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7.6 Software Interrupt Instruction
Execution of the SWI instruction causes an interrupt without an interrupt service re-
quest. SWI is not inhibited by the global mask bits in the CCR, and execution of SWI
sets the I mask bit. Once an SWI interrupt begins, maskable interrupts are inhibited
until the I bit in the CCR is cleared. This typically occurs when an RTI instruction at the
end of the SWI service routine restores context.
7.7 Exception Processing Flow
The first cycle in the exception processing flow for all CPU12 exceptions is the same,
regardless of the source of the exception. Between the first and second cycles of ex-
ecution, the CPU chooses one of three alternative paths. The first path is for resets,
the second path is for pending X or I interrupts, and the third path is used for software
interrupts (SWI) and trapping unimplemented opcodes. The last two paths are virtually
identical, differing only in the details of calculating the return address. Refer to
7-2
for the following discussion.
7.7.1 Vector Fetch
The first cycle of all exception processing, regardless of the cause, is a vector fetch.
The vector points to the address where exception processing will continue. Exception
vectors are stored in a table located at the top of the memory map ($FFC0–$FFFF).
The CPU cannot use the fetched vector until the third cycle of the exception process-
ing sequence.
During the vector fetch cycle, the CPU issues a signal that tells the integration module
to drive the vector address of the highest priority, pending exception onto the system
address bus (the CPU does not provide this address).
After the vector fetch, the CPU selects one of the three alternate execution paths, de-
pending upon the cause of the exception.
7.7.2 Reset Exception Processing
If reset caused the exception, processing continues to cycle 2.0. This cycle sets the X
and I bits in the CCR. The stack pointer is also decremented by two, but this is an ar-
tifact of shared code used for interrupt processing; the SP is not intended to have any
specific value after a reset. Cycles 3.0 through 5.0 are program word fetches that refill
the instruction queue. Fetches start at the address pointed to by the reset vector.
When the fetches are completed, exception processing ends, and the CPU starts ex-
ecuting the instruction at the head of the instruction queue.
MOTOROLA
7-6
EXCEPTION PROCESSING
Figure
CPU12
REFERENCE MANUAL
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