Table of Contents
Advertisement
permitted to execute the STOP instruction or the RESET instruction. To ensure
that a user program cannot enter the supervisor state except in a controlled
manner, the instructions which modify the entire SR are privileged. To aid
in debugging programs to be used in operating systems, the move-to-user-
stack-pointer (MOVE to USP) and move-from-user-stack-pointer (MOVE from
USP) instructions are also privileged.
Once the processor is in the user state and executing instructions, only ex-
ception processing can change the privilege state. During exception proc-
essing, the current state of the S bit in the SR is saved and the S bit is asserted,
putting the processor in the supervisor state. Therefore, when instruction
execution resumes at the address specified to process the exception, the
processor is in the supervisor privilege state. The transition from the super-
visor to user state can be accomplished by any of four instructions: return
from exception (RTE), move to status register (MOVE to SR), AND immediate
to status register (ANDI to SR), and exclusive OR immediate to status register
(EORI to SR).
2.4 EXCEPTION PROCESSING
The processing of an exception occurs in four steps, with variations for dif-
ferent exception causes. During the first step, a temporary copy of the SR is
made, and the SR is set for exception processing. During the second step,
the exception vector is determined; during the third step, the current pro-
cessor context is saved. During the fourth step, a new context is obtained,
and the processor switches to instruction processing.
2.4.1 Exception Vectors
Exception vectors are memory locations from which the processor fetches
the address of a routine to handle that exception. All exception vectors are
two words long except for the reset vector, which is four words. All exception
vectors lie in the supervisor data space except for the reset vector, which is
in the supervisor program space. A vector number is an 8-bit number which,
when multiplied by four, gives the offset of the exception vector. Vector
numbers are generated internally or externally, depending on the cause of
the exception. In the case of interrupts, during the interrupt acknowledge bus
cycle, a peripheral may provide an 8-bit vector number to the processor on
data bus lines D7-DO. Alternatively, the peripheral may assert autovector
(AVEC) instead of data transfer acknowledge (DTACK) to request an auto-
vector for that priority level of interrupt. The exception vector assignments
for the M68000 processor are shown in Table 2-5.
MOTOROLA
MC68302 USER'S MANUAL
2-9
Advertisement
Table of Contents
