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Exceptions are events that require processing outside the normal flow of instruction
execution. This section describes exceptions and the way each is handled.
7.1 Types of Exceptions
CPU12 exceptions include resets, an unimplemented opcode trap, a software interrupt
instruction, X-bit interrupts, and I-bit interrupts. Each exception has an associated 16-
bit vector, which points to the memory location where the routine that handles the ex-
ception is located. As shown in
of the standard 64-Kbyte address map.
The six highest vector addresses are used for resets and unmaskable interrupt sourc-
es. The remaining vectors are used for maskable interrupts. All vectors must be pro-
grammed to point to the address of the appropriate service routine.
The CPU12 can handle up to 64 exception vectors, but the number actually used var-
ies from device to device, and some vectors are reserved for Motorola use. Refer to
device documentation for more information.
Exceptions can be classified by the effect of the X and I interrupt mask bits on recog-
nition of a pending request.
Resets, the unimplemented opcode trap, and the SWI instruction are not affected
by the X and I mask bits.
Interrupt service requests from the XIRQ pin are inhibited when X = 1, but are not
affected by the I bit.
All other interrupts are inhibited when I = 1.
CPU12
REFERENCE MANUAL
SECTION 7
EXCEPTION PROCESSING
Table
Table 7-1 CPU12 Exception Vector Map
Vector Address
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFC0–$FFF1
EXCEPTION PROCESSING
7-1, vectors are stored in the upper 128 bytes
Source
System Reset
Clock Monitor Reset
COP Reset
Unimplemented Opcode Trap
Software Interrupt Instruction (SWI)
XIRQ Signal
IRQ Signal
Device-Specific Interrupt Sources
MOTOROLA
7-1
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