ST STM32L4+ Series Reference Manual page 1944

Serial audio interface (SAI)
Bit 16 FSDEF: Frame synchronization definition.
This bit is set and cleared by software.
0: FS signal is a start frame signal
1: FS signal is a start of frame signal + channel side identification
When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means
that half of this number of slots will be dedicated to the left channel and the other slots for the right
channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...).
This bit is meaningless and is not used in AC'97 or SPDIF audio block configuration. It must be
configured when the audio block is disabled.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 FSALL[6:0]: Frame synchronization active level length.
These bits are set and cleared by software. They specify the length in number of bit clock
(SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame
These bits are meaningless and are not used in AC'97 or SPDIF audio block configuration.
They must be configured when the audio block is disabled.
Bits 7:0 FRL[7:0]: Frame length.
These bits are set and cleared by software. They define the audio frame length expressed in number
of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1.
The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio
block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one
slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000).
In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be
aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not
used (NOMCK = 1), it is recommended to program the frame length to an value ranging from 8 to
256.
These bits are meaningless and are not used in AC'97 or SPDIF audio block configuration.
53.6.8 SAI slot register (SAI_ASLOTR)
Address offset: 0x010
Reset value: 0x0000 0000
Note: This register has no meaning in AC'97 and SPDIF audio protocol.
31 30 29
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15 14 13
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28 27 26 25
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12 11 10 9
NBSLOT[3:0]
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24 23 22 21
SLOTEN[15:0]
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8 7 6 5
SLOTSZ[1:0] Res.
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RM0432 Rev 6
20 19 18 17
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4 3 2 1
FBOFF[4:0]
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RM0432
16
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0
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