ST STM32L4+ Series Reference Manual page 1951

RM0432
Bit 2 WCKCFG: Wrong clock configuration flag.
This bit is read only.
0: Clock configuration is correct
1: Clock configuration does not respect the rule concerning the frame length specification defined in
Section 53.4.6: Frame synchronization
This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NOMCK = 0.
It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register.
This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.
Bit 1 MUTEDET: Mute detection.
This bit is read only.
0: No MUTE detection on the SD input line
1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio
frame
This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a
consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register).
It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register.
This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
Bit 0 OVRUDR: Overrun / underrun.
This bit is read only.
0: No overrun/underrun error.
1: Overrun/underrun error detection.
The overrun and underrun conditions can occur only when the audio block is configured as a
receiver and a transmitter, respectively.
It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register.
This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.
53.6.13 SAI status register (SAI_BSR)
Address offset: 0x038
Reset value: 0x0000 0008
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
(configuration of FRL[7:0] bit in the SAI_xFRCR register)
23 22 21 20
Res. Res. Res. Res.
7 6 5
LFSDE
Res. AFSDET CNRDY
T
r r
RM0432 Rev 6
Serial audio interface (SAI)
19 18
Res.
r
4 3 2
FREQ WCKCFG MUTEDET OVRUDR
r r r
17 16
FLVL[2:0]
r r
1 0
r r
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