ST STM32L4+ Series Reference Manual page 1943

RM0432
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 FSALL[6:0]: Frame synchronization active level length.
These bits are set and cleared by software. They specify the length in number of bit clock
(SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame
These bits are meaningless and are not used in AC'97 or SPDIF audio block configuration.
They must be configured when the audio block is disabled.
Bits 7:0 FRL[7:0]: Frame length.
These bits are set and cleared by software. They define the audio frame length expressed in number
of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1.
The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio
block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one
slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000).
In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be
aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not
used (NOMCK = 1), it is recommended to program the frame length to an value ranging from 8 to
256.
These bits are meaningless and are not used in AC'97 or SPDIF audio block configuration. They
must be configured when the audio block is disabled.
53.6.7 SAI frame configuration register (SAI_BFRCR)
Address offset: 0x02C
Reset value: 0x0000 0007
Note: This register has no meaning in AC'97 and SPDIF audio protocol
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res.
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Bits 31:19 Reserved, must be kept at reset value.
Bit 18 FSOFF: Frame synchronization offset.
This bit is set and cleared by software. It is meaningless and is not used in AC'97 or SPDIF audio
block configuration. This bit must be configured when the audio block is disabled.
0: FS is asserted on the first bit of the slot 0.
1: FS is asserted one bit before the first bit of the slot 0.
Bit 17 FSPOL: Frame synchronization polarity.
This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS
signal. It is meaningless and is not used in AC'97 or SPDIF audio block configuration.
This bit must be configured when the audio block is disabled.
0: FS is active low (falling edge)
1: FS is active high (rising edge)
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
FSALL[6:0]
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23 22 21
Res. Res. Res.
7 6 5
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RM0432 Rev 6
Serial audio interface (SAI)
20 19 18 17
Res. Res. FSOFF FSPOL FSDEF
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4 3 2 1
FRL[7:0]
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16
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0
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