ST STM32L4+ Series Reference Manual page 1932

Serial audio interface (SAI)
53.6 SAI registers
The peripheral registers have to be accessed by words (32 bits).
53.6.1 SAI global configuration register (SAI_GCR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:4 SYNCOUT[1:0]: Synchronization outputs
These bits are set and cleared by software.
00: No synchronization output signals. SYNCOUT[1:0] should be configured as "No synchronization
output signals" when audio block is configured as SPDIF
01: Block A used for further synchronization for others SAI
10: Block B used for further synchronization for others SAI
11: Reserved. These bits must be set when both audio block (A and B) are disabled.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 SYNCIN[1:0]: Synchronization inputs
These bits are set and cleared by software.
Refer to
These bits must be set when both audio blocks (A and B) are disabled.
They are meaningful if one of the two audio blocks is defined to operate in synchronous mode with
an external SAI (SYNCEN[1:0] = 10 in SAI_ACR1 or in SAI_BCR1 registers).
53.6.2 SAI configuration register 1 (SAI_ACR1)
Address offset: 0x004
Reset value: 0x0000 0040
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
OUTD
Res. Res. MONO
RIV
rw rw
1932/2301
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Table 372: External synchronization selection
27 26 25
Res. OSR
rw rw
11 10 9
SYNCEN[1:0] CKSTR LSBFIRST
rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6
Res. Res. Res. SYNCOUT[1:0]
rw
for information on how to program this field.
24 23 22 21
MCKDIV[5:0]
rw rw rw rw
8 7 6 5
DS[2:0]
rw rw rw rw
RM0432 Rev 6
20 19 18
Res. Res. Res.
5 4 3 2
Res. Res.
rw
20 19 18
NOMCK Res.
rw rw
4 3 2
Res. PRTCFG[1:0]
rw rw
RM0432
17 16
Res. Res.
1 0
SYNCIN[1:0]
rw rw
17 16
DMAEN SAIEN
rw rw
1 0
MODE[1:0]
rw rw