ST STM32L4+ Series Reference Manual page 1942

Serial audio interface (SAI)
53.6.6 SAI frame configuration register (SAI_AFRCR)
Address offset: 0x00C
Reset value: 0x0000 0007
Note: This register has no meaning in AC'97 and SPDIF audio protocol.
31 30 29
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15 14 13
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Bits 31:19 Reserved, must be kept at reset value.
Bit 18 FSOFF: Frame synchronization offset.
This bit is set and cleared by software. It is meaningless and is not used in AC'97 or SPDIF audio
block configuration. This bit must be configured when the audio block is disabled.
0: FS is asserted on the first bit of the slot 0.
1: FS is asserted one bit before the first bit of the slot 0.
Bit 17 FSPOL: Frame synchronization polarity.
This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS
signal. It is meaningless and is not used in AC'97 or SPDIF audio block configuration.
This bit must be configured when the audio block is disabled.
0: FS is active low (falling edge)
1: FS is active high (rising edge)
Bit 16 FSDEF: Frame synchronization definition.
This bit is set and cleared by software.
0: FS signal is a start frame signal
1: FS signal is a start of frame signal + channel side identification
When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It
means that half of this number of slots will be dedicated to the left channel and the other slots for the
right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...).
This bit is meaningless and is not used in AC'97 or SPDIF audio block configuration. It must be
configured when the audio block is disabled.
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28 27 26 25
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12 11 10 9
FSALL[6:0]
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24 23 22
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8 7 6
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RM0432 Rev 6
21 20 19 18
Res. Res. Res. FSOFF FSPOL FSDEF
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5 4 3 2
FRL[7:0]
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RM0432
17 16
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1 0
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