Tipb Control Mode Register (Cmr); Register Of The Tipb Bridge; Peripheral Access Timeout - Texas Instruments OMAP5910 Reference Manual

8.6

Peripheral Access Timeout

8.7 TIPB Register
8.7.1 Overview
Table 82. Register of the TIPB Bridge
Name
CMR
†
DSP I/O and MPU byte addresses apply to both OMAP5910 and OMAP5912.
8.7.2

TIPB Control Mode Register (CMR)

SPRU890A
A timeout counter in TIPB bridge module counts how many cycles have
passed since a request was made to access a peripheral. When the counter
reaches 127 (default) DSP subsystem clock cycles, the TIPB bridge module
sends a timeout signal the original requestor. The default timeout value can
be changed with the TIMEOUT bits in the control mode register.
In response to a timeout, the TIPB bridge module sends the timeout signal to
the requestor and sets the bus error bit of the CMR register. In the case of the
DSP core access, the timeout signal sets the bus-error interrupt flag bit in the
DSP core. The DSP core can respond to the interrupt request or ignore the
interrupt request.
The DSP TIPB bridge module is configured through a single register
accessible through the DSP I/O space (see Table 82). The MPU core can also
read the contents of this register.
Description
Control mode register. This register is used to
control the TIPB bridge module.
The control mode register (CMR) indicates the access mode of the MPUI and
the bus error condition status for accesses to the TIPB bridge module. It also
controls DSP core priority versus the MPUI and DSP DMA controller for
accesses to peripherals on the DSP public peripheral bus. This register is
accessible through both the MPU side and the DSP side; however, the MPU
core has read access only. Figure 92 and Table 83 summarize CMR.
TI Peripheral Bus Bridges
DSP I/O MPU Byte
Address † Address
0x0000 0xE100
0000
DSP Subsystem
†
191