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SDRAM Interface
Figure 9–17. SDRAM Refresh
Clock †
CEx
BE[3:0]
EA[15:2]
SDA10
SDRAS
SDCAS
SDWE
† Clock=SDCLK for 'C6201/C6701.
Clock=CLKOUT2 for 'C6202.
Clock=ECLKOUT for 'C6211/C6711.
9.4.4
Mode Register Set
9-28
For all 'C6000 devices, the EMIF SDRAM interface performs CAS-before-
RAS refresh cycles for SDRAM. Some SDRAM manufacturers call this autore-
fresh. Prior to an REFR command, a DCAB command is performed to all CE
spaces specifying SDRAM to ensure that all active banks are closed. Page in-
formation is always invalid before and after a REFR command; thus, a refresh
cycle always forces a page miss. A deactivate cycle is required prior to the re-
fresh command. Figure 9–17 shows the timing diagram for an SDRAM re-
fresh.
The 'C6201/C6202/C6701 EMIF automatically performs a DCAB command
followed by an MRS command whenever the INIT field in the EMIF SDRAM
control register is set. INIT can be set by device reset or by a user write. Like
DCAB and REFR commands, MRS commands are performed to all CE
spaces configured as SDRAM through the MTYPE field. Following a hold, the
external requester should return the SDRAM MRS register's original value be-
fore returning control of the bus to the EMIF. Alternatively, you could poll the
HOLD and HOLDA bits in the EMIF global control register and, upon detecting
completion of an external hold, reinitialize the EMIF by writing a 1 to the INIT bit
in the EMIF SDRAM control register.
The EMIF always uses a mode register value of 0030h during an MRS command.
Figure 9–18 shows the mapping between mode register bits, EMIF pins, and the
REFR
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