L1P Direct Mapped Cache Diagram - Texas Instruments TMS320C6201 Reference Manual

Figure 4–5. L1P Direct Mapped Cache Diagram
Tag Set Offset
Address
Tag RAM
Data out
There are two methods for user-controlled invalidation of data in the L1P. Writ-
ing a 1 to the IP bit of the cache configuration register (CCFG) invalidates all
of the cache tags in the L1P tag RAM. This is a write-only bit, a read of this
bit will always return a 0. Any CPU access to the L1P while invalidation is being
processed stalls the CPU until the invalidation has completed and the CPU re-
quest has been fetched. Figure 4–12 shows the format for the CCFG register.
Table 4–6 describes the operation of this register.
TMS320C6211/C6711 Two-Level Internal Memory
Address
Cache data
Data out
=
L1P Description
L2
data
1 0
Program
data
4-7