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NXP Semiconductors Freescale K22 Reference Manual

NXP Semiconductors Freescale K22 Reference Manual

Supports: mk22fx512vlk12, mk22fn1m0vlk12

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K22 Sub-Family Reference Manual

Supports: MK22FX512VLK12, MK22FN1M0VLK12

Document Number: K22P80M120SF5RM

Rev. 4, November 2014

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Page 1 K22 Sub-Family Reference Manual Supports: MK22FX512VLK12, MK22FN1M0VLK12 Document Number: K22P80M120SF5RM Rev. 4, November 2014...
Page 2 K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Contents Section number Title Page Chapter 1 About This Document Overview..................................53 1.1.1 Purpose.................................53 1.1.2 Audience..............................53 Conventions..................................53 1.2.1 Numbering systems............................53 1.2.2 Typographic notation...........................54 1.2.3 Special terms..............................54 Chapter 2 Introduction Overview..................................55 Module Functional Categories............................55 2.2.1 ARM® Cortex™-M4 Core Modules......................56 2.2.2 System Modules............................57 2.2.3 Memories and Memory Interfaces.......................58 2.2.4...
Page 4 Section number Title Page Core modules................................65 3.2.1 ARM Cortex-M4 Core Configuration......................65 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration..............67 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration............73 3.2.4 JTAG Controller Configuration........................74 System modules................................75 3.3.1 SIM Configuration............................75 3.3.2 System Mode Controller (SMC) Configuration...................76 3.3.3 PMC Configuration............................76 3.3.4...
Page 5 Section number Title Page Memories and memory interfaces..........................94 3.5.1 Flash Memory Configuration........................94 3.5.2 Flash Memory Controller Configuration.....................98 3.5.3 SRAM Configuration...........................99 3.5.4 System Register File Configuration......................102 3.5.5 VBAT Register File Configuration......................103 3.5.6 EzPort Configuration...........................104 3.5.7 FlexBus Configuration..........................105 Security..................................108 3.6.1 CRC Configuration............................108 K22 Sub-Family Reference Manual, Rev.
Page 6 Section number Title Page Analog...................................109 3.7.1 16-bit SAR ADC Configuration........................109 3.7.2 CMP Configuration............................115 3.7.3 12-bit DAC Configuration...........................117 3.7.4 VREF Configuration............................118 Timers...................................119 3.8.1 PDB Configuration............................120 3.8.2 FlexTimer Configuration..........................123 3.8.3 PIT Configuration............................127 3.8.4 Low-power timer configuration........................128 3.8.5 CMT Configuration............................130 3.8.6 RTC configuration............................131 Communication interfaces............................132 3.9.1 Universal Serial Bus (USB) FS Subsystem....................132...
Page 7 Section number Title Page SRAM memory map..............................157 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map..................157 4.5.1 Read-after-write sequence and required serialization of memory operations..........157 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map..................158 4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map..................161 Private Peripheral Bus (PPB) memory map........................165 Chapter 5 Clock Distribution Introduction...................................167...
Page 8 Section number Title Page Chapter 6 Reset and Boot Introduction...................................181 Reset....................................182 6.2.1 Power-on reset (POR)..........................182 6.2.2 System reset sources............................182 6.2.3 MCU Resets..............................186 6.2.4 Reset Pin ..............................188 6.2.5 Debug resets..............................188 Boot....................................189 6.3.1 Boot sources..............................189 6.3.2 Boot options..............................190 6.3.3 FOPT boot options............................190 6.3.4 Boot sequence..............................191 Chapter 7...
Page 9 Section number Title Page 8.3.3 Security Interactions with Debug.........................204 Chapter 9 Debug Introduction...................................207 9.1.1 References..............................209 The Debug Port................................209 9.2.1 JTAG-to-SWD change sequence.........................210 9.2.2 JTAG-to-cJTAG change sequence.......................210 Debug Port Pin Descriptions............................211 System TAP connection..............................211 9.4.1 IR Codes...............................211 JTAG status and control registers..........................212 9.5.1 MDM-AP Control Register..........................213 9.5.2...
Page 10 Section number Title Page Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................223 10.2 Signal Multiplexing Integration............................223 10.2.1 Port control and interrupt module features....................224 10.2.2 PCRn reset values for port A........................224 10.2.3 Clock gating..............................224 10.2.4 Signal multiplexing constraints........................224 10.3 Pinout....................................225 10.3.1 K22 Signal Multiplexing and Pin Assignments...................225 10.3.2...
Page 11 Section number Title Page 11.5 Memory map and register definition..........................245 11.5.1 Pin Control Register n (PORTx_PCRn).......................252 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................254 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................255 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)....................256 11.5.5 Digital Filter Enable Register (PORTx_DFER)...................256 11.5.6 Digital Filter Clock Register (PORTx_DFCR)....................257 11.5.7...
Page 12 Section number Title Page 12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)................282 12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)................284 12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)................287 12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................287 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................290 12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...................291 12.2.18...
Page 13 Section number Title Page 14.3.4 Power Mode Status register (SMC_PMSTAT)...................314 14.4 Functional description..............................314 14.4.1 Power mode transitions..........................314 14.4.2 Power mode entry/exit sequencing......................317 14.4.3 Run modes..............................319 14.4.4 Wait modes..............................321 14.4.5 Stop modes..............................322 14.4.6 Debug in low power modes.........................325 Chapter 15 Power Management Controller (PMC) 15.1 Introduction...................................327 15.2...
Page 14 Section number Title Page 16.3 Memory map/register definition...........................339 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)....................340 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)....................341 16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)....................342 16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)....................343 16.3.5 LLWU Module Enable register (LLWU_ME)....................344 16.3.6 LLWU Flag 1 register (LLWU_F1)......................346 16.3.7...
Page 15 Section number Title Page 17.3 Functional description..............................367 17.3.1 Interrupts..............................367 Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction...................................369 18.1.1 Features................................369 18.2 Memory Map / Register Definition..........................370 18.2.1 Priority Registers Slave (AXBS_PRSn)......................371 18.2.2 Control Register (AXBS_CRSn).........................374 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)..............375 18.3 Functional Description..............................376 18.3.1...
Page 16 Section number Title Page 19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)............394 19.4 Functional description..............................396 19.4.1 Access evaluation macro..........................396 19.4.2 Putting it all together and error terminations....................398 19.4.3 Power management............................398 19.5 Initialization information..............................399 19.6 Application information..............................399 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................403 20.1.1...
Page 17 Section number Title Page 21.5.2 Enabling and configuring sources........................413 Chapter 22 Direct Memory Access Controller (eDMA) 22.1 Introduction...................................417 22.1.1 Block diagram..............................417 22.1.2 Block parts..............................418 22.1.3 Features................................419 22.2 Modes of operation...............................421 22.3 Memory map/register definition...........................421 22.3.1 Control Register (DMA_CR)........................433 22.3.2 Error Status Register (DMA_ES)........................436 22.3.3 Enable Request Register (DMA_ERQ).......................438 22.3.4...
Page 18 Section number Title Page 22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO).......................460 22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES).....................462 22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)..............463 22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................463 22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..............464 22.3.26...
Page 19 Section number Title Page 22.5.7 Dynamic programming..........................491 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................495 23.1.1 Features................................495 23.1.2 Modes of Operation.............................496 23.1.3 Block Diagram.............................497 23.2 EWM Signal Descriptions............................498 23.3 Memory Map/Register Definition..........................498 23.3.1 Control Register (EWM_CTRL).........................498 23.3.2 Service Register (EWM_SERV)........................499 23.3.3 Compare Low Register (EWM_CMPL)......................499 23.3.4...
Page 20 Section number Title Page 24.3.5 Watchdog disabled mode of operation......................510 24.3.6 Debug modes of operation...........................511 24.4 Testing the watchdog..............................511 24.4.1 Quick test..............................512 24.4.2 Byte test................................512 24.5 Backup reset generator..............................513 24.6 Generated resets and interrupts.............................514 24.7 Memory map and register definition..........................514 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)............515 24.7.2...
Page 21 Section number Title Page 25.2 External Signal Description............................529 25.3 Memory Map/Register Definition..........................529 25.3.1 MCG Control 1 Register (MCG_C1)......................530 25.3.2 MCG Control 2 Register (MCG_C2)......................531 25.3.3 MCG Control 3 Register (MCG_C3)......................532 25.3.4 MCG Control 4 Register (MCG_C4)......................533 25.3.5 MCG Control 5 Register (MCG_C5)......................534 25.3.6 MCG Control 6 Register (MCG_C6)......................535 25.3.7...
Page 22 Section number Title Page 26.2 Features and Modes..............................563 26.3 Block Diagram................................564 26.4 OSC Signal Descriptions..............................564 26.5 External Crystal / Resonator Connections........................565 26.6 External Clock Connections............................566 26.7 Memory Map/Register Definitions..........................567 26.7.1 OSC Memory Map/Register Definition.......................567 26.8 Functional Description..............................568 26.8.1 OSC Module States............................568 26.8.2 OSC Module Modes.............................570 26.8.3...
Page 23 Section number Title Page Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction...................................579 28.1.1 Overview..............................579 28.1.2 Features................................580 28.2 Modes of operation...............................580 28.3 External signal description............................580 28.4 Memory map and register descriptions.........................581 28.4.1 Flash Access Protection Register (FMC_PFAPR)..................586 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)..................589 28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)..................592 28.4.4...
Page 24 Section number Title Page 28.4.22 Cache Data Storage (mid-lower word) (FMC_DATAW3SnML)...............605 28.4.23 Cache Data Storage (lowermost word) (FMC_DATAW3SnLM)...............605 28.5 Functional description..............................606 28.5.1 Default configuration...........................606 28.5.2 Configuration options..........................606 28.5.3 Wait states..............................607 28.5.4 Speculative reads............................608 28.6 Initialization and application information........................609 Chapter 29 Flash Memory Module (FTFE) 29.1 Introduction...................................611...
Page 25 Section number Title Page 29.4.9 Flash Program and Erase..........................643 29.4.10 FTFE Command Operations........................643 29.4.11 Margin Read Commands..........................652 29.4.12 Flash command descriptions........................653 29.4.13 Security................................681 29.4.14 Reset Sequence............................683 Chapter 30 EzPort 30.1 Overview..................................685 30.1.1 Block diagram..............................685 30.1.2 Features................................686 30.1.3 Modes of operation............................686 30.2 External signal descriptions............................687 30.2.1...
Page 26 Section number Title Page 31.3.3 Chip Select Control Register (FB_CSCRn)....................704 31.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)..............707 31.4 Functional description..............................708 31.4.1 Modes of operation............................708 31.4.2 Address comparison.............................708 31.4.3 Address driven on address bus........................709 31.4.4 Connecting address/data lines........................709 31.4.5 Bit ordering..............................709 31.4.6 Data transfer signals.............................710 31.4.7...
Page 27 Section number Title Page 32.2.3 CRC Control register (CRC_CTRL)......................746 32.3 Functional description..............................747 32.3.1 CRC initialization/reinitialization........................747 32.3.2 CRC calculations............................748 32.3.3 Transpose feature............................749 32.3.4 CRC result complement..........................751 Chapter 33 Analog-to-Digital Converter (ADC) 33.1 Introduction...................................753 33.1.1 Features................................753 33.1.2 Block diagram..............................754 33.2 ADC Signal Descriptions..............................755 33.2.1 Analog Power (VDDA)..........................756 33.2.2...
Page 28 Section number Title Page 33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............773 33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............773 33.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............774 33.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............774 33.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............775 33.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............775 33.3.18...
Page 29 Section number Title Page 33.5 Initialization information..............................796 33.5.1 ADC module initialization example......................796 33.6 Application information..............................798 33.6.1 External pins and routing..........................798 33.6.2 Sources of error............................800 Chapter 34 Comparator (CMP) 34.1 Introduction...................................805 34.2 CMP features................................805 34.3 6-bit DAC key features..............................806 34.4 ANMUX key features..............................807 34.5 CMP, DAC and ANMUX diagram..........................807 34.6...
Page 30 Section number Title Page 34.13 DAC functional description............................831 34.13.1 Voltage reference source select........................831 34.14 DAC resets..................................831 34.15 DAC clocks...................................831 34.16 DAC interrupts................................832 Chapter 35 12-bit Digital-to-Analog Converter (DAC) 35.1 Introduction...................................833 35.2 Features..................................833 35.3 Block diagram................................833 35.4 Memory map/register definition...........................834 35.4.1 DAC Data Low Register (DACx_DATnL)....................836 35.4.2 DAC Data High Register (DACx_DATnH)....................836...
Page 31 Section number Title Page 36.2 Memory Map and Register Definition..........................846 36.2.1 VREF Trim Register (VREF_TRM)......................846 36.2.2 VREF Status and Control Register (VREF_SC)..................847 36.3 Functional Description..............................848 36.3.1 Voltage Reference Disabled, SC[VREFEN] = 0..................848 36.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..................849 36.4 Initialization/Application Information..........................850 Chapter 37 Programmable Delay Block (PDB)
Page 32 Section number Title Page 37.3.12 Pulse-Out n Delay register (PDBx_POnDLY).....................865 37.4 Functional description..............................865 37.4.1 PDB pre-trigger and trigger outputs......................865 37.4.2 PDB trigger input source selection......................867 37.4.3 DAC interval trigger outputs........................867 37.4.4 Pulse-Out's..............................868 37.4.5 Updating the delay registers.........................868 37.4.6 Interrupts..............................870 37.4.7 DMA................................870 37.5 Application information..............................871...
Page 33 Section number Title Page 38.3.10 Features Mode Selection (FTMx_MODE)....................893 38.3.11 Synchronization (FTMx_SYNC).........................895 38.3.12 Initial State For Channels Output (FTMx_OUTINIT).................898 38.3.13 Output Mask (FTMx_OUTMASK)......................899 38.3.14 Function For Linked Channels (FTMx_COMBINE)...................901 38.3.15 Deadtime Insertion Control (FTMx_DEADTIME)..................906 38.3.16 FTM External Trigger (FTMx_EXTTRIG)....................907 38.3.17 Channels Polarity (FTMx_POL)........................909 38.3.18 Fault Mode Status (FTMx_FMS).........................911...
Page 34 Section number Title Page 38.4.10 Registers updated from write buffers......................951 38.4.11 PWM synchronization..........................953 38.4.12 Inverting...............................969 38.4.13 Software output control..........................971 38.4.14 Deadtime insertion............................973 38.4.15 Output mask..............................976 38.4.16 Fault control..............................977 38.4.17 Polarity control.............................980 38.4.18 Initialization..............................981 38.4.19 Features priority............................981 38.4.20 Channel trigger output..........................982 38.4.21 Initialization trigger............................983 38.4.22...
Page 35 Section number Title Page 39.2 Signal description................................1008 39.3 Memory map/register description..........................1009 39.3.1 PIT Module Control Register (PIT_MCR)....................1009 39.3.2 Timer Load Value Register (PIT_LDVALn)....................1011 39.3.3 Current Timer Value Register (PIT_CVALn).....................1011 39.3.4 Timer Control Register (PIT_TCTRLn)......................1012 39.3.5 Timer Flag Register (PIT_TFLGn)......................1013 39.4 Functional description..............................1013 39.4.1 General operation............................1013...
Page 36 Section number Title Page 40.4.3 LPTMR prescaler/glitch filter........................1026 40.4.4 LPTMR compare............................1027 40.4.5 LPTMR counter............................1027 40.4.6 LPTMR hardware trigger..........................1028 40.4.7 LPTMR interrupt............................1028 Chapter 41 Carrier Modulator Transmitter (CMT) 41.1 Introduction...................................1031 41.2 Features..................................1031 41.3 Block diagram................................1032 41.4 Modes of operation...............................1033 41.4.1 Wait mode operation............................1034 41.4.2 Stop mode operation............................1035 41.5...
Page 37 Section number Title Page 41.7 Functional description..............................1046 41.7.1 Clock divider..............................1046 41.7.2 Carrier generator............................1046 41.7.3 Modulator..............................1049 41.7.4 Extended space operation..........................1053 41.8 CMT interrupts and DMA............................1055 Chapter 42 Real Time Clock (RTC) 42.1 Introduction...................................1057 42.1.1 Features................................1057 42.1.2 Modes of operation............................1057 42.1.3 RTC Signal Descriptions..........................1058 42.2 Register definition.................................1059 42.2.1...
Page 38 Section number Title Page 42.3 Functional description..............................1075 42.3.1 Power, clocking, and reset...........................1075 42.3.2 Time counter..............................1076 42.3.3 Compensation...............................1077 42.3.4 Time alarm..............................1077 42.3.5 Update mode..............................1078 42.3.6 Monotonic counter............................1078 42.3.7 Register lock..............................1079 42.3.8 Access control..............................1079 42.3.9 Interrupt................................1079 Chapter 43 Universal Serial Bus OTG Controller (USBOTG) 43.1 Introduction...................................1081 43.1.1...
Page 39 Section number Title Page 43.4.5 OTG Interrupt Status register (USBx_OTGISTAT)..................1095 43.4.6 OTG Interrupt Control Register (USBx_OTGICR)..................1096 43.4.7 OTG Status register (USBx_OTGSTAT)....................1097 43.4.8 OTG Control register (USBx_OTGCTL)....................1098 43.4.9 Interrupt Status register (USBx_ISTAT).....................1099 43.4.10 Interrupt Enable register (USBx_INTEN)....................1100 43.4.11 Error Interrupt Status register (USBx_ERRSTAT)..................1101 43.4.12 Error Interrupt Enable register (USBx_ERREN)..................1102 43.4.13...
Page 40 Section number Title Page Chapter 44 USB Device Charger Detection Module (USBDCD) 44.1 Preface...................................1121 44.1.1 References..............................1121 44.1.2 Acronyms and abbreviations........................1121 44.1.3 Glossary...............................1122 44.2 Introduction...................................1122 44.2.1 Block diagram..............................1122 44.2.2 Features................................1123 44.2.3 Modes of operation............................1123 44.3 Module signal descriptions............................1124 44.4 Memory map/Register definition..........................1125 44.4.1 Control register (USBDCD_CONTROL)....................1126 44.4.2...
Page 41 Section number Title Page Chapter 45 USB Voltage Regulator 45.1 Introduction...................................1153 45.1.1 Overview..............................1153 45.1.2 Features................................1154 45.1.3 Modes of Operation.............................1155 45.2 USB Voltage Regulator Module Signal Descriptions....................1155 Chapter 46 CAN (FlexCAN) 46.1 Introduction...................................1157 46.1.1 Overview..............................1158 46.1.2 FlexCAN module features...........................1159 46.1.3 Modes of operation............................1160 46.2 FlexCAN signal descriptions............................1162 46.2.1...
Page 42 Section number Title Page 46.3.13 Error and Status 2 register (CANx_ESR2)....................1189 46.3.14 CRC Register (CANx_CRCR)........................1191 46.3.15 Rx FIFO Global Mask register (CANx_RXFGMASK)................1191 46.3.16 Rx FIFO Information Register (CANx_RXFIR)..................1192 46.3.17 Rx Individual Mask Registers (CANx_RXIMRn)..................1193 46.3.34 Message buffer structure..........................1194 46.3.35 Rx FIFO structure............................1200 46.4 Functional description..............................1202 46.4.1...
Page 43 Section number Title Page 47.1.4 Modes of Operation.............................1238 47.2 Module signal descriptions............................1240 47.2.1 PCS0/SS — Peripheral Chip Select/Slave Select..................1240 47.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3...................1240 47.2.3 PCS4 — Peripheral Chip Select 4........................1240 47.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe.............1241 47.2.5 SIN —...
Page 44 Section number Title Page 47.4.7 Interrupts/DMA requests..........................1277 47.4.8 Power saving features..........................1280 47.5 Initialization/application information...........................1281 47.5.1 How to manage queues..........................1281 47.5.2 Switching Master and Slave mode.......................1282 47.5.3 Initializing Module in Master/Slave Modes....................1282 47.5.4 Baud rate settings............................1282 47.5.5 Delay settings...............................1283 47.5.6 Calculation of FIFO pointer addresses......................1284 Chapter 48 Inter-Integrated Circuit (I2C) 48.1...
Page 45 Section number Title Page 48.4 Functional description..............................1302 48.4.1 I2C protocol..............................1302 48.4.2 10-bit address...............................1307 48.4.3 Address matching............................1309 48.4.4 System management bus specification......................1310 48.4.5 Resets................................1312 48.4.6 Interrupts..............................1312 48.4.7 Programmable input glitch filter........................1315 48.4.8 Address matching wakeup...........................1315 48.4.9 DMA support...............................1315 48.5 Initialization/application information...........................1316 Chapter 49 Universal Asynchronous Receiver/Transmitter (UART) 49.1...
Page 46 Section number Title Page 49.3.11 UART Control Register 4 (UARTx_C4).....................1344 49.3.12 UART Control Register 5 (UARTx_C5).....................1345 49.3.13 UART Extended Data Register (UARTx_ED)....................1346 49.3.14 UART Modem Register (UARTx_MODEM).....................1347 49.3.15 UART Infrared Register (UARTx_IR)......................1348 49.3.16 UART FIFO Parameters (UARTx_PFIFO)....................1349 49.3.17 UART FIFO Control Register (UARTx_CFIFO)..................1350 49.3.18 UART FIFO Status Register (UARTx_SFIFO)...................1351 49.3.19...
Page 47 Section number Title Page 49.4.7 ISO-7816/smartcard support........................1387 49.4.8 Infrared interface............................1392 49.5 Reset....................................1393 49.6 System level interrupt sources............................1393 49.6.1 RXEDGIF description..........................1394 49.7 DMA operation................................1395 49.8 Application information..............................1395 49.8.1 Transmit/receive data buffer operation......................1395 49.8.2 ISO-7816 initialization sequence.........................1396 49.8.3 Initialization sequence (non ISO-7816).......................1398 49.8.4 Overrun (OR) flag implications........................1399 49.8.5...
Page 48 Section number Title Page 50.4.3 Command Argument register (SDHC_CMDARG)..................1413 50.4.4 Transfer Type register (SDHC_XFERTYP)....................1413 50.4.5 Command Response 0 (SDHC_CMDRSP0)....................1417 50.4.6 Command Response 1 (SDHC_CMDRSP1)....................1418 50.4.7 Command Response 2 (SDHC_CMDRSP2)....................1418 50.4.8 Command Response 3 (SDHC_CMDRSP3)....................1418 50.4.9 Buffer Data Port register (SDHC_DATPORT)...................1420 50.4.10 Present State register (SDHC_PRSSTAT)....................1420 50.4.11...
Page 49 Section number Title Page 50.5.6 SDIO card interrupt............................1473 50.5.7 Card insertion and removal detection......................1475 50.5.8 Power management and wakeup events.......................1476 50.5.9 MMC fast boot.............................1477 50.6 Initialization/application of SDHC..........................1479 50.6.1 Command send and response receive basic operation.................1479 50.6.2 Card Identification mode..........................1480 50.6.3 Card access..............................1485 50.6.4...
Page 50 Section number Title Page 51.3 Memory map and register definition..........................1515 51.3.1 SAI Transmit Control Register (I2Sx_TCSR).....................1517 51.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................1520 51.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)................1520 51.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)................1522 51.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)................1523 51.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)................1524 51.3.7...
Page 51 Section number Title Page 51.4.7 Interrupts and DMA requests........................1545 Chapter 52 General-Purpose Input/Output (GPIO) 52.1 Introduction...................................1547 52.1.1 Features................................1547 52.1.2 Modes of operation............................1547 52.1.3 GPIO signal descriptions..........................1548 52.2 Memory map and register definition..........................1549 52.2.1 Port Data Output Register (GPIOx_PDOR)....................1551 52.2.2 Port Set Output Register (GPIOx_PSOR)....................1551 52.2.3 Port Clear Output Register (GPIOx_PCOR)....................1552 52.2.4...
Page 52 Section number Title Page 53.3 Register description..............................1561 53.3.1 Instruction register............................1561 53.3.2 Bypass register.............................1561 53.3.3 Device identification register........................1561 53.3.4 Boundary scan register..........................1562 53.4 Functional description..............................1563 53.4.1 JTAGC reset configuration..........................1563 53.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1563 53.4.3 TAP controller state machine........................1563 53.4.4 JTAGC block instructions..........................1565 53.4.5...
Page 53: About This Document
1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K22 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the microcontroller in a system.
Page 54: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 55: Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1.
Page 56: Arm® Cortex™-M4 Core Modules
Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description Memories • Internal memories include: • Program flash memory • On devices with FlexMemory: FlexMemory • FlexNVM • FlexRAM • On devices with program flash only: Programming acceleration RAM •...
Page 57: System Modules
Chapter 2 Introduction Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM Cortex-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures.
Page 58: Memories And Memory Interfaces
Module Functional Categories Table 2-3. System modules (continued) Module Description Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details. Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave.
Page 59: Clocks
Chapter 2 Introduction Table 2-4. Memories and memory interfaces (continued) Module Description Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industry- standard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming.
Page 60: Analog Modules
Module Functional Categories 2.2.6 Analog modules The following analog modules are available on this device: Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) 16-bit successive-approximation ADC Analog comparators Compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed.
Page 61: Communication Interfaces
Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description Flexible timer modules (FTM) • Selectable FTM source clock, programmable prescaler • 16-bit counter supporting free-running or initial/final value, and counting is up or up-down • Input capture, output compare, and edge-aligned and center-aligned PWM modes •...
Page 62: Human-Machine Interfaces
Orderable part numbers Table 2-9. Communication modules Module Description USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes. Includes an on-chip transceiver for full and low speeds. USB Device Charger Detect (USBDCD) The USBDCD monitors the USB data lines to detect a smart charger meeting the USB Battery Charging Specification Rev1.2.
Page 63 Chapter 2 Introduction Table 2-11. Orderable part numbers summary Freescale part number Package Total Program EEPROM SRAM GPIO count flash flash frequenc memory MK22FX512VLK12 120 MHz LQFP 640 KB 512 KB 4 KB 128 KB MK22FN1M0VLK12 120 MHz LQFP 1 MB 1 MB —...
Page 64 Orderable part numbers K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 65: Chip Configuration
Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and •...
Page 66: K22 Sub-Family Reference Manual, Rev. 4, November
Core modules Debug Interrupts ARM Cortex-M4 Crossbar switch Core Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock distribution Power management...
Page 67: Nested Vectored Interrupt Controller (Nvic) Configuration
Chapter 3 Chip Configuration 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK. This results in the following: • The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock.
Page 68 Core modules Interrupts Module Nested Vectored Module Interrupt Controller (NVIC) Module Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored ARM Cortex-M4 Technical Reference Manual Interrupt Controller (NVIC) System memory map System memory map Clocking Clock distribution...
Page 69 Chapter 3 Chip Configuration • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus The IRQ number is used within ARM's NVIC documentation. Table 3-4.
Page 70 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0070 DMA channel 12 transfer complete 0x0000_0074 DMA channel 13 transfer complete 0x0000_0078 DMA channel 14 transfer complete 0x0000_007C DMA channel 15 transfer complete 0x0000_0080 DMA error interrupt channels 0-15...
Page 71 Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_00D8 UART3 Single interrupt vector for UART error sources 0x0000_00DC ADC0 — 0x0000_00E0 CMP0 — 0x0000_00E4 CMP1 —...
Page 72 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0164 ADC1 — 0x0000_0168 — 0x0000_016C CAN0 OR'ed Message buffer (0-15) 0x0000_0170 CAN0 Bus Off 0x0000_0174 CAN0 Error 0x0000_0178 CAN0 Transmit Warning 0x0000_017C...
Page 73: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Chapter 3 Chip Configuration • NVICIABR1 • NVICIPR14 • To determine the particular IRQ's bitfield location within these particular registers: • NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit location = IRQ mod 32 = 26 • NVICIPR14 bitfield starting location = 8 * (IRQ mod 4) + 4 = 20 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14...
Page 74: Jtag Controller Configuration
Core modules Table 3-6. Reference links to related information (continued) Topic Related module Reference Nested Vectored NVIC Interrupt Controller (NVIC) Wake-up requests AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7.
Page 75: System Modules
Chapter 3 Chip Configuration JTAG controller Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 76: System Mode Controller (Smc) Configuration
System modules 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access System Mode Resets Controller (SMC) Figure 3-6.
Page 77: Low-Leakage Wake-Up Unit (Llwu) Configuration
Chapter 3 Chip Configuration Peripheral bridge Register access Module Module signals signals Power Management Controller (PMC) Figure 3-7. PMC configuration Table 3-11. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Full description System Mode...
Page 78 System modules Peripheral bridge 0 Register access Wake-up requests Low-Leakage Wake-up Module Unit (LLWU) Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-12. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Clocking Clock distribution Power management...
Page 79: Mcm Configuration
Chapter 3 Chip Configuration Table 3-13. Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P14 PTD4/LLWU_P14 pin LLWU_P3 PTA4/LLWU_P3 pin LLWU_P15 PTD6/LLWU_P15 pin LLWU_P4 PTA13/LLWU_P4 pin LLWU_M0IF...
Page 80: Crossbar Switch Configuration
System modules 3.3.6 Crossbar Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Master Modules Slave Modules Crossbar Switch ARM core code bus Flash controller ARM core...
Page 81 Chapter 3 Chip Configuration Table 3-15. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Memory protection Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core Crossbar switch master DMA controller DMA controller Crossbar switch master EzPort EzPort Crossbar switch master...
Page 82: Memory Protection Unit (Mpu) Configuration
System modules Slave module Slave port number Protected by MPU? Peripheral bridge 1/GPIO No. Protection built into bridge. FlexBus 1. See System memory map for access restrictions. 3.3.6.3 PRS register reset values The AXBS_PRSn registers reset to 0043_0210h. 3.3.7 Memory Protection Unit (MPU) Configuration This section summarizes how the module has been configured in the chip.
Page 83 Chapter 3 Chip Configuration 3.3.7.1 MPU Slave Port Assignments The memory-mapped resources protected by the MPU are: Table 3-17. MPU Slave Port Assignments Source MPU Slave Port Assignment Destination Crossbar slave port 0 MPU slave port 0 Flash Controller Crossbar slave port 1 MPU slave port 1 SRAM backdoor Code Bus...
Page 84 System modules Table 3-19. Access Violation Indications (continued) Bus Master Core Indication SDHC Interrupt vector #97 3.3.7.4 Reset Values for RGD0 Registers At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire 4 GB address space with read, write and execute permissions given to the core, debugger and the DMA bus masters.
Page 85: Peripheral Bridge Configuration
Chapter 3 Chip Configuration Table 3-21. Write Access to RGD0 Registers Bus Master Write Access? Core Partial. The Core cannot write to the following registers or register fields: • RGD0_WORD0, RGD0_WORD1, RGD0_WORD3 • RGD0_WORD2[M1SM, M1UM] • RGDAAC0[M1SM, M1UM] NOTE: Changes to the RGD0_WORD2 alterable fields should be done via a write to RGDAAC0.
Page 86: Dma Request Multiplexer Configuration
System modules 3.3.8.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map AIPS1 Memory Map for the memory slot assignment for each module. 3.3.9 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip.
Page 87 Chapter 3 Chip Configuration Table 3-24. DMA request sources - MUX 0 Source Source module Source description number — Channel disabled Reserved Not used UART0 Receive UART0 Transmit UART1 Receive UART1 Transmit UART2 Receive UART2 Transmit UART3 Receive UART3 Transmit Reserved —...
Page 88: Dma Controller Configuration
System modules Table 3-24. DMA request sources - MUX 0 (continued) Source Source module Source description number FTM3 Channel 7 ADC0 — ADC1 — CMP0 — CMP1 — CMP2 — DAC0 — Reserved — — — Port control module Port A Port control module Port B Port control module...
Page 89: External Watchdog Monitor (Ewm) Configuration
Chapter 3 Chip Configuration Peripheral bridge 0 Register access Transfers Requests DMA Controller Figure 3-14. DMA Controller configuration Table 3-25. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map System memory map Register access Peripheral bridge AIPS-Lite 0...
Page 90 System modules Peripheral bridge 0 Register access Module signals External Watchdog Monitor (EWM) Figure 3-15. External Watchdog Monitor configuration Table 3-26. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) System memory map System memory map Clocking Clock distribution Power management...
Page 91: Watchdog Configuration
Chapter 3 Chip Configuration 3.3.11.3 EWM_OUT pin state in low power modes During Wait, Stop, and Power Down modes the EWM_OUT pin preserve its state before entering Wait or Stop mode. When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode.
Page 92: Clock Modules
Clock modules Table 3-30. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.12.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes.
Page 93: Osc Configuration
Chapter 3 Chip Configuration Peripheral bridge Register access Multipurpose Clock Generator (MCG) Figure 3-17. MCG configuration Table 3-32. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control...
Page 94: Rtc Osc Configuration
Memories and memory interfaces Table 3-33. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details.
Page 95: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Transfers Flash memory Figure 3-20. Flash memory configuration Table 3-35. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers...
Page 96 Memories and memory interfaces • 2 blocks (512 KB each) blocks of program flash consisting of 4 KB sectors • 1 block of programming Acceleration RAM • For devices that contain FlexNVM: • 1 block (512 KB) of program flash consisting of 4 KB sectors •...
Page 97 Chapter 3 Chip Configuration 3.5.1.4 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field...
Page 98: Flash Memory Controller Configuration
Memories and memory interfaces 3.5.1.7 Erase All Flash Contents An Erase All Flash Blocks operation can be launched by software through a series of peripheral bus writes to flash registers. In addition the entire flash memory may be erased external to the flash memory from the SWJ-DP debug port by setting DAP_CONTROL[0].
Page 99: Sram Configuration
Chapter 3 Chip Configuration Table 3-36. Reference links to related information (continued) Topic Related module Reference Transfers Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters.
Page 100 Memories and memory interfaces Cortex-M4 SRAM upper core Transfers Crossbar SRAM lower switch Figure 3-24. SRAM configuration Table 3-37. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller...
Page 101 Chapter 3 Chip Configuration • SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF • SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1] This is illustrated in the following figure. 0x2000_0000 – SRAM_size/2 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size/2 - 1 Figure 3-25. SRAM blocks memory map For example, for a device containing 64 KB of SRAM the ranges are: •...
Page 102: System Register File Configuration
Memories and memory interfaces • SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor port. • SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the backdoor port. The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA).
Page 103: Vbat Register File Configuration
Chapter 3 Chip Configuration 3.5.4 System Register File Configuration This section summarizes how the module has been configured in the chip. Peripheral bridge 0 Register access Register file Figure 3-27. System Register file configuration Table 3-38. Reference links to related information Topic Related module Reference...
Page 104: Ezport Configuration
Memories and memory interfaces Peripheral bridge Register access VBAT register file Figure 3-28. VBAT Register file configuration Table 3-39. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management...
Page 105: Flexbus Configuration
Chapter 3 Chip Configuration Table 3-40. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.6.1 JTAG instruction The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode.
Page 106 Memories and memory interfaces Peripheral bridge 0 Register access Module signals Transfers FlexBus Figure 3-30. FlexBus configuration Table 3-41. Reference links to related information Topic Related module Reference Full description FlexBus FlexBus System memory map System memory map Clocking Clock distribution Power management Power management Transfers...
Page 107 Chapter 3 Chip Configuration FlexBus Port Control Module CSPMCR FB_ALE FB_CS1 Group1 FB_TS Reserved FB_CS4 FB_TSIZ0 Group2 FB_BE_31_24 Reserved FB_CS5 FB_TSIZ1 Group3 FB_BE_23_16 Reserved FB_TBST FB_CS2 Group4 FB_BE_15_8 Reserved FB_TA FB_CS3 Group5 FB_BE_7_0 Reserved Figure 3-31. FlexBus control signal multiplexing K22 Sub-Family Reference Manual, Rev.
Page 108: Security
Security Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function.
Page 109: Analog
Chapter 3 Chip Configuration Peripheral bridge Register access Figure 3-32. CRC configuration Table 3-42. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip.
Page 110 Analog Table 3-43. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains two ADCs. 3.7.1.1.1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package.
Page 111 Chapter 3 Chip Configuration 3.7.1.3.1.1 ADC0 Channel Assignment for 80-Pin Package ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0 00001 DAD1 Reserved Reserved 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3...
Page 112 Analog 3. Interleaved with ADC1_DP0 and ADC1_DM0 4. Interleaved with ADC1_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC1_SE8 7. Interleaved with ADC1_SE9 8. Interleaved with ADC1_DM3 9.
Page 113 Chapter 3 Chip Configuration ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 10010 AD18 Reserved VREF Output 10011 AD19 Reserved ADC1_DM0 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved Reserved 11000 AD24...
Page 114 Analog 3.7.1.6 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. ADC0 ADC0_SE8/ADC1_SE8 ADC0_SE9/ADC1_SE9 ADC1 Figure 3-35. ADC hardware interleaved channels integration 3.7.1.7 ADC Reference Options The ADC supports the following references: •...
Page 115 Chapter 3 Chip Configuration 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled).
Page 116: Cmp Configuration
Analog 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals Other peripherals Figure 3-36. CMP configuration Table 3-45.
Page 117: 12-Bit Dac Configuration
Chapter 3 Chip Configuration 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: • VREF_OUT - V input • VDD - V input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing.
Page 118: Vref Configuration
Analog 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input.
Page 119: Timers
Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Module signals Transfers VREF Other peripherals Figure 3-38. VREF configuration Table 3-47. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management...
Page 120: Pdb Configuration
Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Register access Module signals Transfers Other peripherals Figure 3-39.
Page 121 Chapter 3 Chip Configuration 3.8.1.1.2 PDB Input Trigger Connections Table 3-50. PDB Input Trigger Options PDB Trigger PDB Input 0000 External Trigger 0001 CMP 0 0010 CMP 1 0011 CMP 2 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111...
Page 122 Timers • PDB channel 1 pre-trigger 0 acknowledgement input: ADC0SC1B_COCO • PDB channel 1 pre-trigger 1 acknowledgement input: ADC1SC1A_COCO So, the back-to-back chain is connected as a ring: Channel 0 pre-trigger 0 Channel 1 Channel 0 pre-trigger 1 pre-trigger 1 Channel 1 pre-trigger 0 Figure 3-40.
Page 123: Flextimer Configuration
Chapter 3 Chip Configuration 3.8.1.6 Pulse-Out Connection Individual PDB Pulse-Out signals are connected to each CMP block and used for sample window. 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level.
Page 124 Timers 3.8.2.1 Instantiation Information This device contains four FlexTimer modules. The following table shows how these modules are configured. Table 3-53. FTM Instantiations FTM instance Number of channels Features/usage FTM0 3-phase motor + 2 general purpose or stepper motor FTM1 Quadrature decoder or general purpose FTM2 Quadrature decoder or general purpose...
Page 125 Chapter 3 Chip Configuration 3.8.2.5 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SOPT4 register in the SIM module. The external pin option is selected by default. • FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output •...
Page 126 Timers For the triggers with more than one option, the SOPT4 register in the SIM module controls the selection. 3.8.2.7 Input capture options for FTM module instances The following channel 0 input capture source options are selected via the SOPT4 register in the SIM module.
Page 127: Pit Configuration
Chapter 3 Chip Configuration FTM1 CONF Register GTBEOUT = 0 FTM0 FTM Counter GTBEEN = 1 CONF Register gtb_in gtb_in GTBEOUT = 1 FTM Counter GTBEEN = 1 FTM2 gtb_out CONF Register GTBEOUT = 0 FTM Counter GTBEEN = 1 gtb_in FTM3 CONF Register...
Page 128: Low-Power Timer Configuration
Timers Peripheral bridge Register access Periodic interrupt timer Figure 3-43. PIT configuration Table 3-54. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below.
Page 129 Chapter 3 Chip Configuration Peripheral bridge Register access Module signals Low-power timer Figure 3-44. LPTMR configuration Table 3-56. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management...
Page 130: Cmt Configuration
Timers 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin Reserved 3.8.5 CMT Configuration...
Page 131: Rtc Configuration
Chapter 3 Chip Configuration 3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin.
Page 132: Communication Interfaces
Communication interfaces RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-47. RTC_CLKOUT generation 3.9 Communication interfaces 3.9.1 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host.
Page 133 Chapter 3 Chip Configuration potential clock glitches which may result in USB enumeration stage failure. 1. Select the USB clock source by configuring SIM_SOPT2. 2. Select the desired clock divide ratio by configuring SIM_CLKDIV2. 3. Enable USB clock gate by setting SIM_SCGC4. 3.9.1.1 USB Wakeup When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set.
Page 134 Communication interfaces 2 AA Cells To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP USB0_DM Controller XCVR Figure 3-49. USB regulator AA cell usecase 3.9.1.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD.
Page 135 Chapter 3 Chip Configuration To PMC and Pads VOUT33 stab Chip TYPE A VREGIN VBUS Si2301 Charger Regulator USB0_DP Controller XCVR USB0_DM Li-Ion VBUS Sense Charger Detect Figure 3-50. USB regulator Li-ion usecase 3.9.1.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD.
Page 136 Communication interfaces 3.9.1.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals Transfers USB controller Figure 3-52.
Page 137 Chapter 3 Chip Configuration Peripheral bridge 0 Register access USB Device Charger Detect Figure 3-53. USB DCD configuration Table 3-60. Reference links to related information Topic Related module Reference Full description USB DCD USB DCD System memory map System memory map Clocking Clock Distribution USB FS/LS controller...
Page 138: Can Configuration
Communication interfaces NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.2 CAN Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 139 Chapter 3 Chip Configuration 3.9.2.3 FlexCAN Clocking 3.9.2.3.1 Clocking Options CAN_CTRL1[CLKSRC] register bit selects between clocking the FlexCAN from the internal bus clock or the input clock (OSCERCLK). 3.9.2.3.2 Clock Gating The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits. These bits are cleared after any reset, which disables the clock to the corresponding module.
Page 140: Spi Configuration
Communication interfaces 3.9.2.5 FlexCAN Operation in Low Power Modes The FlexCAN module is operational in VLPR and VLPW modes. With the 2 MHz bus clock, the fastest supported FlexCAN transfer rate is 256 kbps. With the 4 MHz bus clock, the fastest supported FlexCAN transfer rate is 512 kbps.The bit timing parameters in the module must be adjusted for the new frequency, but full functionality is possible.
Page 141 Chapter 3 Chip Configuration 3.9.3.1 SPI Modules Configuration This device contains two SPI modules . 3.9.3.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2.
Page 142 Communication interfaces 3.9.3.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-66. SPI PCS signals SPI Module PCS Signals SPI0 SPI1 3.9.3.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional;...
Page 143: I2C Configuration
Chapter 3 Chip Configuration 3.9.3.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. 3.9.3.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller.
Page 144: Uart Configuration
Communication interfaces Peripheral bridge Register access Module signals Figure 3-57. I2C configuration Table 3-68. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.4.1 Number of I2C modules...
Page 145 Chapter 3 Chip Configuration Peripheral bridge Register access Module signals UART Figure 3-58. UART configuration Table 3-69. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control...
Page 146 Communication interfaces 3.9.5.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.5.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source...
Page 147: Sdhc Configuration
Chapter 3 Chip Configuration Source UART 0 UART 1 UART 2 UART 3 Block wait timer — — — (ISO7816) Guard time violation — — — (ISO7816) 3.9.6 SDHC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 148: I2S Configuration
Communication interfaces • OSCERCLK • Bypass clock from off-chip (SDHC0_CLKIN) NOTE SDHC0_CLKIN is not available on all packages. See the Pinout section for more information. 3.9.6.2 SD bus pullup/pulldown constraints The SD standard requires the SD bus signals (except the SD clock) to be pulled up during data transfers.
Page 149 Chapter 3 Chip Configuration 3.9.7.1 Instantiation information This device contains one I S module. As configured on the device, module features include: • TX data lines: 2 • RX data lines: 2 • FIFO size (words): 8 • Maximum words per frame: 32 •...
Page 150 Communication interfaces The module's MCLK Divide Register (MDR) configures the MCLK divide ratio. The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE]) controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0, and the pin is the output from the clock divider when MOE is 1.
Page 151: Human-Machine Interfaces
Chapter 3 Chip Configuration In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame.
Page 152 Human-machine interfaces Table 3-72. Reference links to related information (continued) Topic Related module Reference Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 GPIO access protection The GPIO module does not have access protection because it is not connected to a peripheral bridge slot and is not protected by the MPU.
Page 153: Memory Map
Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. This map provides the complete architectural address space definition for the various sections.
Page 154: Aliased Bit-Band Regions
System memory map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0x2200_0000–0x23FF_FFFF Aliased to TCMU SRAM bitband Cortex-M4 core only 0x2400_0000–0x3FFF_FFFF Reserved – 0x4000_0000–0x4007_FFFF Bitband region for AIPS0 Cortex-M4 core & DMA/EzPort 0x4008_0000–0x400F_EFFF Bitband region for AIPS1 Cortex-M4 core &...
Page 155: Flash Memory Map
Chapter 4 Memory Map • Writing a value with bit 0 set writes a 1 to the target bit. • Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: •...
Page 156: Alternate Non-Volatile Irc User Trim Description
Flash Memory Map Flash memory base address Registers Program flash base address Flash configuration field Program flash Programming acceleration RAM base address Figure 4-2. Flash memory map for devices containing only program flash Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address...
Page 157: Sram Memory Map
Chapter 4 Memory Map 4.4 SRAM memory map The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Arrays for details.
Page 158: Read-After-Write Sequence And Required Serialization Of Memory Operations
Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map 4.5.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: • Exiting an interrupt service routine (ISR) •...
Page 159 Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4001_5000 — 0x4001_6000 — 0x4001_7000 — 0x4001_8000 — 0x4001_9000 — 0x4001_A000 — 0x4001_B000 — 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 Flash memory controller 0x4002_0000 Flash memory...
Page 160 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4003_C000 — 0x4003_D000 Real-time clock (RTC) 0x4003_E000 VBAT register file 0x4003_F000 DAC0 0x4004_0000 Low-power timer (LPTMR) 0x4004_1000 System register file 0x4004_2000 —...
Page 161: Peripheral Bridge 1 (Aips-Lite 1) Memory Map
Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4006_3000 — 0x4006_4000 Multi-purpose Clock Generator (MCG) 0x4006_5000 System oscillator (OSC) 0x4006_6000 0x4006_7000 0x4006_8000 — 0x4006_9000 — 0x4006_A000 UART 0 0x4006_B000 UART 1 0x4006_C000 UART 2...
Page 162: Peripheral Bridge 1 (Aips-Lite 1) Memory Map
Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map 4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map Table 4-3. Peripheral bridge 1 slot assignments System 32-bit base address Slot Module number 0x4008_0000 Peripheral bridge 1 (AIPS-Lite 1) 0x4008_1000 — 0x4008_2000 — 0x4008_3000 —...
Page 163 Chapter 4 Memory Map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400A_5000 — 0x400A_6000 — 0x400A_7000 — 0x400A_8000 — 0x400A_9000 — 0x400A_A000 — 0x400A_B000 — 0x400A_C000 — 0x400A_D000 — 0x400A_E000 — 0x400A_F000 0x400B_0000 —...
Page 164 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400C_C000 12-bit digital-to-analog converter (DAC) 0 0x400C_D000 — 0x400C_E000 — 0x400C_F000 — 0x400D_0000 — 0x400D_1000 — 0x400D_2000 — 0x400D_3000 —...
Page 165: Private Peripheral Bus (Ppb) Memory Map
Chapter 4 Memory Map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400F_3000 — 0x400F_4000 — 0x400F_5000 — 0x400F_6000 — 0x400F_7000 — 0x400F_8000 — 0x400F_9000 — 0x400F_A000 — 0x400F_B000 — 0x400F_C000 — 0x400F_D000 —...
Page 166 Private Peripheral Bus (PPB) memory map Table 4-4. PPB memory map (continued) System 32-bit Address Range Resource 0xE008_1000–0xE008_1FFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 167: Clock Distribution
Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory . The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules.
Page 168: Clock Definitions
Clock definitions Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 4 MHz IRC FCRDIV Clock options for MCGIRCLK some peripherals MCGFFCLK 32 kHz IRC (see note) Core / system clocks OUTDIV1 Bus clock OUTDIV2 MCGOUTCLK FlexBus clock OUTDIV3...
Page 169: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1. Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external...
Page 170 Clock definitions Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency FlexBus clock Up to 50 MHz Up to 4 MHz MCGOUTCLK clock In all stop modes or divider (FB_CLK) FlexBus disabled...
Page 171: Internal Clocking Requirements
Chapter 5 Clock Distribution 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module’s CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1.
Page 172: Vlpr Mode Clocking
Clock Gating To enable the low power boot option program FTF_FOPT[LPBOOT] to zero. During the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode.
Page 173 Chapter 5 Clock Distribution Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks ARM Cortex-M4 core System clock Core clock — NVIC System clock — — System clock — — System clock — — System clock TRACE clock TRACE_CLKOUT System clock...
Page 174: Pmc 1-Khz Lpo Clock
Module clocks Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks LPTMR Flash clock LPO, OSCERCLK, — MCGIRCLK, ERCLK32K Bus clock — — Flash clock EXTAL32 — Communication interfaces USB FS OTG System clock USB FS clock —...
Page 175: Debug Trace Clock
Chapter 5 Clock Distribution WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.3 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. MCGOUTCLK TPIU TRACECLKIN TRACE_CLKOUT ÷2 Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3.
Page 176: Lptmr Clocking
Module clocks Bus clock PORTx digital input filter clock PORTx_DFCR[CS] Figure 5-4. PORTx digital input filter clock generation 5.7.5 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes.
Page 177: Flexcan Clocking
Chapter 5 Clock Distribution The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. USB_CLKIN USB 48MHz SIM_CLKDIV2 MCGPLLCLK or [USBFRAC, USBDIV] MCGFLLCLK SIM_SOPT2[USBSRC] Figure 5-6. USB 48 MHz clock source NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification.
Page 178: Sdhc Clocking
Module clocks 5.7.9 SDHC clocking The SDHC module has four possible clock sources for the external clock source, as shown in the following figure. Core / system clock MCGPLLCLK or MCGFLLCLK SDHC clock OSCERCLK SDHC0_CLKIN SIM_SOPT2[SDHCSRC] Figure 5-8. SDHC clock generation NOTE SDHC0_CLKIN is not available on all packages.
Page 179: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 5 Clock Distribution I2S/SAI Clock Generation MCLK_OUT I2Sx_TCR2/RCR2 BCLK_OUT MCGPLLCLK Fractional Clock OSC0ERCLK MCLK Clock Divider SYSCLK BCLK MCLK_IN BUSCLK Divider BCLK_IN [MSEL] [DIV] [BCD] I2Sx_MCR[MOE] I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] Figure 5-9. I S/SAI clock generation K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 180 Module clocks K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 181: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •...
Page 182: Reset
Reset 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition.
Page 183 Chapter 6 Reset and Boot Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device.
Page 184 Reset 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage.
Page 185 Chapter 6 Reset and Boot 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below f or f , as controlled by the C2[RANGE] field loc_low...
Page 186: Mcu Resets
Reset 6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set.
Page 187 Chapter 6 Reset and Boot 6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources.
Page 188: Reset Pin
Reset 6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
Page 189: Boot
Chapter 6 Reset and Boot 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: •...
Page 190: Boot Options
Boot 6.3.2 Boot options The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset. The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions.
Page 191: Boot Sequence
Chapter 6 Reset and Boot Table 6-3. Flash Option Register Bit Definitions (continued) Field Value Definition EZPORT_DIS Enable/disable EzPort function. EzPort operation is disabled. The device always boots to normal CPU execution and the state of EZP_CS signal during reset is ignored. This option avoids inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI function.
Page 192 Boot EzPort mode can be disabled by programming the FOPT[EZPORT_DIS] field in the Flash Memory module. 5. When Flash Initialization completes, the RESET pin is observed. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset.
Page 193: Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power Modes Description The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory.
Page 194 Power Modes Description Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait - Allows peripherals to function while the core is in sleep mode, reducing Sleep Interrupt via WFI power. NVIC remains sensitive to interrupts; peripherals continue to be clocked.
Page 195: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLLS0 (Very Most peripherals are disabled (with clocks stopped), but LLWU and Sleep Deep Wakeup Reset Low Leakage RTC can be used. NVIC is disabled; LLWU is used to wake up. Stop 0) All of SRAM_U and SRAM_L are powered off.
Page 196: Power Mode Transitions
Power mode transitions If the oscillator was configured to continue running during VLLSx modes, it must be re- configured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured.
Page 197: Power Modes Shutdown Sequencing
Chapter 7 Power Management Any reset VLPW Wait VLPR Stop VLPS VLLS 3, 2, 1, 0 Figure 7-1. Power mode state transition diagram 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state.
Page 198: Module Operation In Low Power Modes
Module Operation in Low Power Modes • Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. • Polls stop acknowledge indications from the non-core crossbar masters (DMA), supporting peripherals (SPI, PIT) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode.
Page 199 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx LLWU static static static static Regulator low power low power low power low power low power in VLLS2/3, OFF in VLLS0/1 disabled disabled disabled...
Page 200 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx USB FS/LS static static static static static USB DCD static static static USB Voltage optional optional optional optional optional optional Regulator UART...
Page 201: Clock Gating
Chapter 7 Power Management 7. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 8. System OSC and LPO clock sources are not available in VLLS0 9. RTC_CLKOUT is not available. 10. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares.
Page 202 Clock Gating K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 203: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits.
Page 204: Security Interactions With Other Modules
Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface.
Page 205: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 206 Security Interactions with other Modules K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 207: Introduction
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: •...
Page 208 Introduction Cortex-M4 INTNMI Interrupts Sleep INTISR[239:0] NVIC Core SLEEPING Debug Trigger SLEEPDEEP Instr. Data Trace port (serial wire or multi-pin) TPIU AWIC Private Peripheral Bus (internal) Table I-code bus Code bus D-code bus Matrix System bus SWJ-DP AHB-AP JTAG MDM-AP Figure 9-1.
Page 209: References
Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description DWT (Data and Address Watchpoints) 4 data and address watchpoints FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
Page 210: Jtag-To-Swd Change Sequence
The Debug Port IR==BYPASS or IDC ODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] To Test J TAGC Resources nTRST TC K TRACESWO (1’b1 = 4-pin J TAG) CJ TAG (1’b0 = 2-pin cJ TAG) TDI TDO PEN nSYS_TDO nSYS_TDI 1’b1 nTRST nSYS_TRST SWCLKTCK TC K nSYS_TC K...
Page 211: Debug Port Pin Descriptions
Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities.
Page 212: Ir Codes
JTAG status and control registers 9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation...
Page 213: Mdm-Ap Control Register
Chapter 9 Debug Table 9-4. MDM-AP Register Summary (continued) 0x0100_0000 Status MDM-AP Status Register 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0000 DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SWJ-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP)
Page 214 JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset.
Page 215: Mdm-Ap Status Register
Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Name Secure Description Timestamp Disable Set this bit to disable the 48-bit global trace timestamp counter during debug halt mode when the core is halted. 0 The timestamp counter continues to count assuming trace is enabled and the ETM is enabled.
Page 216: Debug Resets
Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Name Description LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted.
Page 217: Ahb-Ap
Chapter 9 Debug • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command. • System POR reset Conversely the debug system is capable of generating system reset using the following mechanism: •...
Page 218: Itm
9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets.
Page 219: Coresight Embedded Trace Buffer (Etb)
Chapter 9 Debug • one reduced function counter • two external inputs • a 24-byte FIFO queue • global timestamping 9.11 Coresight Embedded Trace Buffer (ETB) The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from any CoreSight-compliant component trace source with an ATB master port, such as a trace source or a trace funnel.
Page 220: Performance Profiling With The Etb
TPIU 9.11.1 Performance Profiling with the ETB To create a performance profile (e.g. gprof) for the target application, a means to collect trace over a long period of time is needed. The ETB buffer is too small to capture a meaningful profile in just one take.
Page 221: Debug In Low Power Modes
Chapter 9 Debug • It contains four comparators that you can configure as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT.
Page 222: Debug Module State In Low Power Modes
Debug & Security In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode.
Page 223: Signal Multiplexing And Signal Descriptions
Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.
Page 224: Port Control And Interrupt Module Features
Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details.
Page 225: Pinout
Chapter 10 Signal Multiplexing and Signal Descriptions 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.1 K22 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document.
Page 226 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTE3 ADC0_DM2/ ADC0_DM2/ PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD TRACE_D1 SPI1_SOUT ADC1_SE7a ADC1_SE7a PTE4/ DISABLED PTE4/ SPI1_PCS0 UART3_TX SDHC0_D3 TRACE_D0 LLWU_P2 LLWU_P2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0 USB0_DP USB0_DP...
Page 227 Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2C2_SCL I2S0_TXD0 FTM1_QD_ PTA13/ CMP2_IN1 CMP2_IN1 PTA13/ CAN0_RX FTM1_CH1 I2C2_SDA I2S0_TX_FS FTM1_QD_ LLWU_P4 LLWU_P4 PTA14 DISABLED PTA14...
Page 228: K22 Pinouts
Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ALT2 I2S0_RXD0 FB_AD10 CMP0_OUT FTM0_CH2 LLWU_P9 LLWU_P9 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK FB_AD9 I2S0_MCLK LLWU_P10 LLWU_P10 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ I2S0_RX_FS...
Page 229: Module Signal Description Tables
Chapter 10 Signal Multiplexing and Signal Descriptions PTE0 PTE1/LLWU_P0 PTE2/LLWU_P1 PTC3/LLWU_P7 PTE3 PTC2 PTE4/LLWU_P2 PTC1/LLWU_P6 PTE5 PTC0 PTB19 PTB18 USB0_DP PTB17 USB0_DM PTB16 VOUT33 VREGIN ADC0_DP0/ADC1_DP3 PTB11 ADC0_DM0/ADC1_DM3 PTB10 ADC1_DP0/ADC0_DP3 PTB3 ADC1_DM0/ADC0_DM3 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-2.
Page 230: Core Modules
Module Signal Description Tables 10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal Description name JTAG_TMS JTAG_TMS/ JTAG Test Mode Selection SWD_DIO JTAG_TCLK JTAG_TCLK/ JTAG Test Clock SWD_CLK JTAG_TDI JTAG_TDI JTAG Test Data Input JTAG_TDO JTAG_TDO/ JTAG Test Data Output TRACE_SWO JTAG_TRST...
Page 231: Clock Modules
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-6. EWM Signal Descriptions Chip signal name Module signal Description name EWM_IN EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low.
Page 232 Module Signal Description Tables Table 10-10. FlexBus Signal Descriptions Chip signal name Module signal Description name CLKOUT FB_CLK FlexBus Clock Output FB_AD[31:0] FB_D31–FB_D0 Data Bus—During the first cycle, this bus drives the upper address byte, addr[31:24]. When FlexBus is used in a nonmultiplexed configuration, this is the data bus, FB_D.
Page 233 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal Description name FB_TSIZ[1:0] FB_TSIZ1–FB_TSIZ0 Transfer Size—Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports.
Page 234: Analog
Module Signal Description Tables Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal Description name FB_TA FB_TA Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated.
Page 235 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-11. ADC 0 Signal Descriptions (continued) Chip signal name Module signal Description name VREFH Voltage Reference Select High REFSH VREFL Voltage Reference Select Low REFSL VDDA Analog Power Supply VSSA Analog Ground Table 10-12.
Page 236: Timer Modules
Module Signal Description Tables Table 10-16. DAC 0 Signal Descriptions Chip signal name Module signal Description name DAC0_OUT — DAC output Table 10-17. VREF Signal Descriptions Chip signal name Module signal Description name VREF_OUT VREF_OUT Internally-generated Voltage Reference output 10.4.6 Timer Modules Table 10-18.
Page 237 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-20. FTM 2 Signal Descriptions (continued) Chip signal name Module signal Description name FTM2_QD_PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. FTM2_QD_PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B.
Page 238: Communication Interfaces
Module Signal Description Tables 10.4.7 Communication Interfaces Table 10-26. USB FS OTG Signal Descriptions Chip signal name Module signal Description name USB0_DM usb_dm USB D- analog data signal on the USB bus. USB0_DP usb_dp USB D+ analog data signal on the USB bus. USB_CLKIN —...
Page 239 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-30. SPI 1 Signal Descriptions (continued) Chip signal name Module signal Description name SPI1_SIN Serial Data In SPI1_SOUT SOUT Serial Data Out SPI1_SCK Master mode: Serial Clock (output) Table 10-31. I C 0 Signal Descriptions Chip signal name Module signal Description...
Page 240 Module Signal Description Tables Table 10-35. UART 3 Signal Descriptions Chip signal name Module signal Description name UART3_CTS Clear to send UART3_RTS Request to send UART3_TX Transmit data UART3_RX Receive data Table 10-36. SDHC Signal Descriptions Chip signal name Module signal Description name SDHC0_DCLK...
Page 241: Human-Machine Interfaces (Hmi)
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.8 Human-Machine Interfaces (HMI) Table 10-38. GPIO Signal Descriptions Chip signal name Module signal Description name PTA[31:0] PORTA31–PORTA0 General-purpose input/output PTB[31:0] PORTB31–PORTB0 General-purpose input/output PTC[31:0] PORTC31–PORTC0 General-purpose input/output PTD[31:0] PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1.
Page 242 Module Signal Description Tables K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 243: Port Control And Interrupts (Port)
Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 11.2 Overview The port control and interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
Page 244: Modes Of Operation
Overview • Digital input filter for each pin, usable by any digital peripheral muxed onto the • Individual enable or bypass control field per pin • Selectable clock source for digital input filter with a five bit resolution on filter size •...
Page 245: External Signal Description
Chapter 11 Port control and interrupts (PORT) 11.2.2.4 Debug mode In Debug mode, PORT operates normally. 11.3 External signal description The following table describes the PORT external signal. Table 11-1. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device.
Page 246: K22 Sub-Family Reference Manual, Rev. 4, November
Memory map and register definition PORT memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_9000 Pin Control Register n (PORTA_PCR0) See section 11.5.1/252 4004_9004 Pin Control Register n (PORTA_PCR1) See section 11.5.1/252 4004_9008 Pin Control Register n (PORTA_PCR2) See section 11.5.1/252...
Page 247 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 0000_0000h 11.5.5/256 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 0000_0000h 11.5.6/257 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 0000_0000h 11.5.7/257...
Page 248 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A084 Global Pin Control High Register (PORTB_GPCHR) (always 0000_0000h 11.5.3/255 reads 0) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 0000_0000h 11.5.4/256 4004_A0C0 Digital Filter Enable Register (PORTB_DFER)
Page 249 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B07C Pin Control Register n (PORTC_PCR31) See section 11.5.1/252 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) (always 0000_0000h 11.5.2/254...
Page 250 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C070 Pin Control Register n (PORTD_PCR28) See section 11.5.1/252 4004_C074 Pin Control Register n (PORTD_PCR29) See section 11.5.1/252 4004_C078 Pin Control Register n (PORTD_PCR30) See section 11.5.1/252...
Page 251 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D064 Pin Control Register n (PORTE_PCR25) See section 11.5.1/252 4004_D068 Pin Control Register n (PORTE_PCR26) See section 11.5.1/252 4004_D06C Pin Control Register n (PORTE_PCR27) See section...
Page 252: Pin Control Register N (Portx_Pcrn)
Memory map and register definition 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE Refer to the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package.
Page 253 Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag.
Page 254: Global Pin Control Low Register (Portx_Gpclr)
Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. High drive strength is configured on the corresponding pin, if pin is configured as a digital output. Open Drain Enable Open drain configuration is valid in all digital pin muxing modes.
Page 255: Global Pin Control High Register (Portx_Gpchr)
Chapter 11 Port control and interrupts (PORT) PORTx_GPCLR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. Corresponding Pin Control Register is not updated with the value in GPWD.
Page 256: Interrupt Status Flag Register (Portx_Isfr)
Memory map and register definition 11.5.4 Interrupt Status Flag Register (PORTx_ISFR) The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location.
Page 257: Digital Filter Clock Register (Portx_Dfcr)
Chapter 11 Port control and interrupts (PORT) PORTx_DFER field descriptions (continued) Field Description The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field.
Page 258: Functional Description
Functional description Address: Base address + C8h offset FILT Reset PORTx_DFWR field descriptions Field Description 31–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 4–0 Filter Length FILT The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters.
Page 259: Global Pin Control
Chapter 11 Port control and interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, digital output buffer enable, digital input buffer enable, and passive filter enable. A lock field also exists that allows the configuration for each pin to be locked until the next system reset.
Page 260: Digital Filter
Functional description The interrupt status flag is set when the configured edge or level is detected on the pin or at the output of the digital input filter, if the digital input digital filter is enabled. When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition.
Page 261: System Integration Module (Sim)
Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.1 Features Features of the SIM include: •...
Page 262: Memory Map And Register Definition
Memory map and register definition 12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers.
Page 263: System Options Register 1 (Sim_Sopt1)
Chapter 12 System Integration Module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h OSC32KSEL Reset RAMSIZE Reserved Reset * Notes: • Reset value loaded during System Reset from Flash IFR. •...
Page 264 Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. USB voltage regulator in standby mode during VLPR and VLPW modes USBVSTBY Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes.
Page 265: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Chapter 12 System Integration Module (SIM) 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS. Address: 4004_7000h base + 4h offset = 4004_7004h Reset Reset SIM_SOPT1CFG field descriptions Field Description 31–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 266: System Options Register 2 (Sim_Sopt2)
Memory map and register definition SIM_SOPT1CFG field descriptions (continued) Field Description 23–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–0 This field is reserved.
Page 267 Chapter 12 System Integration Module (SIM) SIM_SOPT2 field descriptions (continued) Field Description 27–26 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 25–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–22 This field is reserved.
Page 268: System Options Register 4 (Sim_Sopt4)
Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description Selects the clock to output on the CLKOUT pin. FlexBus CLKOUT Reserved Flash clock LPO clock (1 kHz) MCGIRCLK RTC 32.768kHz clock OSCERCLK0 Reserved RTC clock out select RTCCLKOUTSEL Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin.
Page 269 Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description Reserved FTM2 channel match drives FTM3 hardware trigger 1 FlexTimer 3 Hardware Trigger 0 Source Select FTM3TRG0SRC Selects the source of FTM3 hardware trigger 0. Reserved FTM1 channel match drives FTM3 hardware trigger 0 FlexTimer 0 Hardware Trigger 1 Source Select FTM0TRG1SRC Selects the source of FTM0 hardware trigger 1.
Page 270 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description FTM_CLK0 pin FTM_CLK1 pin This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 21–20 FTM2 channel 0 input capture source select FTM2CH0SRC...
Page 271: System Options Register 5 (Sim_Sopt5)
Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description Selects the source of FTM1 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. FTM1_FLT0 pin CMP0 out This field is reserved.
Page 272 Memory map and register definition SIM_SOPT5 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–6 UART 1 receive data source select UART1RXSRC Selects the source for the UART 1 receive data. UART1_RX pin CMP0 CMP1...
Page 273: System Options Register 7 (Sim_Sopt7)
Chapter 12 System Integration Module (SIM) 12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Reset ADC1TRGSEL ADC0TRGSEL Reset SIM_SOPT7 field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC1 alternate trigger enable ADC1ALTTRGEN Enable alternative conversion triggers for ADC1.
Page 274 Memory map and register definition SIM_SOPT7 field descriptions (continued) Field Description 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 FTM3 trigger 1100 RTC alarm 1101 RTC seconds 1110 Low-power timer trigger 1111 Reserved ADC0 alternate trigger enable...
Page 275: System Device Identification Register (Sim_Sdid)
Chapter 12 System Integration Module (SIM) 12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h REVID DIEID FAMID PINID 0 x* x* x* x* 0 0 x* x* x* x* x* x* x* Reset * Notes: •...
Page 276: System Clock Gating Control Register 1 (Sim_Scgc1)
Memory map and register definition SIM_SDID field descriptions (continued) Field Description 1011 Custom pinout (WLCSP) 1100 Reserved 1101 Reserved 1110 256-pin 1111 Reserved 12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1) Address: 4004_7000h base + 1028h offset = 4004_8028h Reset I2C2 Reset SIM_SCGC1 field descriptions...
Page 277: System Clock Gating Control Register 2 (Sim_Scgc2)
Chapter 12 System Integration Module (SIM) SIM_SCGC1 field descriptions (continued) Field Description Clock disabled Clock enabled 5–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2) DAC0 can be accessed through both AIPS0 and AIPS1.
Page 278: System Clock Gating Control Register 3 (Sim_Scgc3)
Memory map and register definition SIM_SCGC2 field descriptions (continued) Field Description 8–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 279 Chapter 12 System Integration Module (SIM) SIM_SCGC3 field descriptions (continued) Field Description Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. FTM3 Clock Gate Control FTM3 This bit controls the clock gate to the FTM3 module. Clock disabled Clock enabled FTM2 Clock Gate Control...
Page 280: System Clock Gating Control Register 4 (Sim_Scgc4)
Memory map and register definition 12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h VREF CMP Reset I2C1 I2C0 CMT EWM Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 1.
Page 281: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 12 System Integration Module (SIM) SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled UART2 Clock Gate Control UART2 This bit controls the clock gate to the UART2 module. Clock disabled Clock enabled UART1 Clock Gate Control UART1 This bit controls the clock gate to the UART1 module.
Page 282: System Clock Gating Control Register 5 (Sim_Scgc5)
Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Reset Reset SIM_SCGC5 field descriptions...
Page 283 Chapter 12 System Integration Module (SIM) SIM_SCGC5 field descriptions (continued) Field Description Clock disabled Clock enabled Port B Clock Gate Control PORTB This bit controls the clock gate to the Port B module. Clock disabled Clock enabled Port A Clock Gate Control PORTA This bit controls the clock gate to the Port A module.
Page 284: System Clock Gating Control Register 6 (Sim_Scgc6)
Memory map and register definition 12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6) DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3. When accessing through AIPS0, define the clock gate control bits in SCGC6.
Page 285 Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description FTM2 Clock Gate Control FTM2 This bit controls the clock gate to the FTM2 module. Clock disabled Clock enabled FTM1 Clock Gate Control FTM1 This bit controls the clock gate to the FTM1 module. Clock disabled Clock enabled FTM0 Clock Gate Control...
Page 286 Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. SPI1 Clock Gate Control SPI1 This bit controls the clock gate to the SPI1 module. Clock disabled Clock enabled SPI0 Clock Gate Control...
Page 287: System Clock Gating Control Register 7 (Sim_Scgc7)
Chapter 12 System Integration Module (SIM) 12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Reset Reset SIM_SCGC7 field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 288 Memory map and register definition NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. Address: 4004_7000h base + 1044h offset = 4004_8044h OUTDIV1 OUTDIV2 OUTDIV3 OUTDIV4 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: •...
Page 289 Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 23–20 Clock 3 output divider value OUTDIV3 This field sets the divide value for the FlexBus clock (external pin FB_CLK) from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 depending on FTF_FOPT[LPBOOT].
Page 290: System Clock Divider Register 2 (Sim_Clkdiv2)
Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 15–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2) Address: 4004_7000h base + 1048h offset = 4004_8048h Reset USBDIV...
Page 291: Flash Configuration Register 1 (Sim_Fcfg1)
Chapter 12 System Integration Module (SIM) 12.2.17 Flash Configuration Register 1 (SIM_FCFG1) For devices with FlexNVM: The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command. For devices with program flash only: The EESIZE and DEPART filelds are not applicable.
Page 292 Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 0111 128 KB of FlexNVM 1001 256 KB of FlexNVM 1011 512 KB of FlexNVM 1111 512 KB of FlexNVM 27–24 Program flash size PFSIZE This field specifies the amount of program flash memory available on the device . Undefined values are reserved.
Page 293 Chapter 12 System Integration Module (SIM) SIM_FCFG1 field descriptions (continued) Field Description vectors do not need to be relocated out of Flash memory. The wakeup time from Wait mode is extended when this bit is set. Flash remains enabled during Wait mode Flash is disabled for the duration of Wait mode Flash Disable FLASHDIS...
Page 294: Flash Configuration Register 2 (Sim_Fcfg2)
Memory map and register definition 12.2.18 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 MAXADDR1 Reset Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_FCFG2 field descriptions Field Description Swap program flash SWAPPFLSH For devices without FlexNVM: Indicates that swap is active .
Page 295: Unique Identification Register High (Sim_Uidh)
Chapter 12 System Integration Module (SIM) SIM_FCFG2 field descriptions (continued) Field Description This field concatenated with 13 trailing zeros indicates the first invalid address of flash block 0 (program flash 0). For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0.
Page 296: Unique Identification Register Mid-High (Sim_Uidmh)
Memory map and register definition 12.2.20 Unique Identification Register Mid-High (SIM_UIDMH) Address: 4004_7000h base + 1058h offset = 4004_8058h 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: •...
Page 297: Unique Identification Register Low (Sim_Uidl)
Chapter 12 System Integration Module (SIM) 12.2.22 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: •...
Page 298 Functional description K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 299: Reset Control Module (Rcm)
Chapter 13 Reset Control Module (RCM) 13.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 13.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control.
Page 300: System Reset Status Register 0 (Rcm_Srs0)
Reset memory map and register descriptions 13.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: •...
Page 301: System Reset Status Register 1 (Rcm_Srs1)
Chapter 13 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for information on the loss-of-clock event. Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock.
Page 302 Reset memory map and register descriptions Address: 4007_F000h base + 1h offset = 4007_F001h Read SACKERR EZPT MDM_AP LOCKUP JTAG Write Reset RCM_SRS1 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 303: Reset Pin Filter Control Register (Rcm_Rpfc)
Chapter 13 Reset Control Module (RCM) 13.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode.
Page 304: Reset Pin Filter Width Register (Rcm_Rpfw)
Reset memory map and register descriptions 13.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Read RSTFLTSEL Write...
Page 305: Mode Register (Rcm_Mr)
Chapter 13 Reset Control Module (RCM) RCM_RPFW field descriptions (continued) Field Description 11001 Bus clock filter count is 26 11010 Bus clock filter count is 27 11011 Bus clock filter count is 28 11100 Bus clock filter count is 29 11101 Bus clock filter count is 30 11110...
Page 306 Reset memory map and register descriptions K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 307: System Mode Controller (Smc)
Chapter 14 System Mode Controller (SMC) 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
Page 308 Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways.
Page 309: Memory Map And Register Descriptions
Chapter 14 System Mode Controller (SMC) Table 14-1. Power modes (continued) Mode Description The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic.
Page 310: Power Mode Protection Register (Smc_Pmprot)
Memory map and register descriptions SMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_E002 VLLS Control register (SMC_VLLSCTRL) 14.3.3/313 4007_E003 Power Mode Status register (SMC_PMSTAT) 14.3.4/314 14.3.1 Power Mode Protection register (SMC_PMPROT) This register provides protection for entry into any low-power run or stop mode.
Page 311: Power Mode Control Register (Smc_Pmctrl)
Chapter 14 System Mode Controller (SMC) SMC_PMPROT field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Allow Low-Leakage Stop Mode ALLS Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter any low-leakage stop mode (LLS).
Page 312 Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field Description Causes the SMC to exit to normal RUN mode when any active MCU interrupt occurs while in a VLP mode (VLPR, VLPW or VLPS). NOTE: If VLPS mode was entered directly from RUN mode, the SMC will always exit back to normal RUN mode regardless of the LPWUI setting.
Page 313: Vlls Control Register (Smc_Vllsctrl)
Chapter 14 System Mode Controller (SMC) 14.3.3 VLLS Control register (SMC_VLLSCTRL) The VLLSCTRL register controls features related to VLLS modes. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS.
Page 314: Power Mode Status Register (Smc_Pmstat)
Functional description 14.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS.
Page 315 Chapter 14 System Mode Controller (SMC) Any RESET VLPW VLPR WAIT STOP VLPS VLLS 3, 2, 1, 0 Figure 14-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-7. Power mode transition triggers Transition # From Trigger conditions...
Page 316 Functional description Table 14-7. Power mode transition triggers (continued) Transition # From Trigger conditions STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode.
Page 317: Power Mode Entry/Exit Sequencing
Chapter 14 System Mode Controller (SMC) Table 14-7. Power mode transition triggers (continued) Transition # From Trigger conditions VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. VLLSx Wakeup from enabled LLWU input source or RESET pin VLPR...
Page 318 Functional description Reset Control Low - Module Leakage (RCM) Wakeup (LLWU) Stop/Wait LP exit LP exit System Bus masters low power bus (non-CPU) Clock Mode CCM low power bus Control Bus slaves low power bus Controller Module (SMC) (CCM) PMC low power bus Flash low power bus MCG enable System...
Page 319: Run Modes
Chapter 14 System Mode Controller (SMC) 14.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1.
Page 320 Functional description 14.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 •...
Page 321: Wait Modes
Chapter 14 System Mode Controller (SMC) To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
Page 322: Stop Modes
Functional description In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM.
Page 323 Chapter 14 System Mode Controller (SMC) • Low-Leakage Stop (LLS) • Very-Low-Leakage Stop (VLLSx) 14.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running.
Page 324 Functional description 14.4.5.3 Low-Leakage Stop (LLS) mode Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: • In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and •...
Page 325: Debug In Low Power Modes
Chapter 14 System Mode Controller (SMC) • In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and • The device is configured as shown in Table 14-7. In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off.
Page 326 Functional description No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all of the debug controls and settings to be powered off.
Page 327: Power Management Controller (Pmc)
Chapter 15 Power Management Controller (PMC) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 15.2 Features The PMC features include: •...
Page 328: Lvd Reset Operation
Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point;...
Page 329: I/O Retention
Chapter 15 Power Management Controller (PMC) 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode.
Page 330: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
Memory map and register descriptions 15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Page 331: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chapter 15 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field Description Low-Voltage Detect Reset Enable LVDRE This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 3–2 This field is reserved.
Page 332: Regulator Status And Control Register (Pmc_Regsc)
Memory map and register descriptions PMC_LVDSC2 field descriptions Field Description Low-Voltage Warning Flag LVWF This read-only status bit indicates a low-voltage warning event. LVWF is set when V transitions below Supply the trip point, or after reset and V is already below V .
Page 333 Chapter 15 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Read ACKISO REGONS Reserved BGEN Reserved BGBE Write Reset PMC_REGSC field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 334 Memory map and register descriptions K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 335: Low-Leakage Wakeup Unit (Llwu)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes.
Page 336: Modes Of Operation
Introduction • External pin wakeup inputs, each of which is programmable as falling-edge, rising- edge, or any change • Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect and RESET pin detect.
Page 337: Block Diagram
Chapter 16 Low-Leakage Wakeup Unit (LLWU) When the RESET pin filter or wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means that there is no restart to the minimum LPO cycle duration as the filtering transitions from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter.
Page 338: Llwu Signal Descriptions
LLWU signal descriptions enter low leakge mode WUME7 LLWU_MWUF7 occurred Interrupt module Module7 interrupt flag flag detect (LLWU_M7IF) Internal module sources LLWU_MWUF0 occurred Interrupt module Module0 interrupt flag flag detect (LLWU_M0IF) FILT1[FILTSEL] WUME0 FILT1[FILTE] LLWU_P15 Pin filter 1 wakeup occurred Edge Synchronizer Pin filter 1...
Page 339: Memory Map/Register Definition
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.3 Memory map/register definition The LLWU includes the following registers: • Wakeup source enable registers • Enable external pin input sources • Enable internal peripheral sources • Wakeup flag registers • Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt •...
Page 340: Llwu Pin Enable 1 Register (Llwu_Pe1)
Memory map/register definition 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
Page 341: Llwu Pin Enable 2 Register (Llwu_Pe2)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE1 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4.
Page 342: Llwu Pin Enable 3 Register (Llwu_Pe3)
Memory map/register definition LLWU_PE2 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 1–0 Wakeup Pin Enable For LLWU_P4 WUPE4 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 343: Llwu Pin Enable 4 Register (Llwu_Pe4)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P9 WUPE9 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 344: Llwu Module Enable Register (Llwu_Me)
Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P14 WUPE14 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 345 Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions Field Description Wakeup Module Enable For Module 7 WUME7 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 6 WUME6 Enables an internal module as a wakeup source input.
Page 346: Llwu Flag 1 Register (Llwu_F1)
Memory map/register definition 16.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit.
Page 347: Llwu Flag 2 Register (Llwu_F2)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F1 field descriptions (continued) Field Description Wakeup Flag For LLWU_P4 WUF4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source Wakeup Flag For LLWU_P3...
Page 348 Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
Page 349: Llwu Flag 3 Register (Llwu_F3)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F2 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF10. LLWU_P10 input was not a wakeup source LLWU_P10 input was a wakeup source Wakeup Flag For LLWU_P9 WUF9...
Page 350 Memory map/register definition LLWU_F3 field descriptions Field Description Wakeup flag For module 7 MWUF7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 7 input was not a wakeup source Module 7 input was a wakeup source Wakeup flag For module 6...
Page 351: Llwu Pin Filter 1 Register (Llwu_Filt1)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 0 input was not a wakeup source Module 0 input was a wakeup source 16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital...
Page 352: Llwu Pin Filter 2 Register (Llwu_Filt2)
Memory map/register definition LLWU_FILT1 field descriptions (continued) Field Description 3–0 Filter Pin Select FILTSEL Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter 1111 Select LLWU_P15 for filter 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin.
Page 353: Llwu Reset Enable Register (Llwu_Rst)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT2 field descriptions (continued) Field Description 3–0 Filter Pin Select FILTSEL Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter 1111 Select LLWU_P15 for filter 16.3.11 LLWU Reset Enable register (LLWU_RST) LLWU_RST is a control register that is used to enable/disable the digital filter for the external pin detect and RESET pin.
Page 354: Functional Description
Functional description 16.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module.
Page 355: Vlls Modes
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written.
Page 356 Functional description K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 357: Miscellaneous Control Module (Mcm)
Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: •...
Page 358: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory map/register descriptions MCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) E008_000C Control Register (MCM_CR) 0000_0000h 17.2.3/360 E008_0010 Interrupt Status Register (MCM_ISCR) 0000_0000h 17.2.4/362 E008_0014 ETB Counter Control register (MCM_ETBCC) 0000_0000h 17.2.5/365 E008_0018 ETB Reload register (MCM_ETBRL)
Page 359: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
Chapter 17 Miscellaneous Control Module (MCM) 17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Read Write Reset MCM_PLAMC field descriptions...
Page 360: Control Register (Mcm_Cr)
Memory map/register descriptions 17.2.3 Control Register (MCM_CR) CR defines the arbitration and protection schemes for the two system RAM arrays. Address: E008_0000h base + Ch offset = E008_000Ch SRAMLAP SRAMUAP Reserved Reset Reserved Reserved Reset MCM_CR field descriptions Field Description This field is reserved.
Page 361 Chapter 17 Miscellaneous Control Module (MCM) MCM_CR field descriptions (continued) Field Description SRAM_U write protect SRAMUWP When this bit is set, writes to SRAM_U array generates a bus error. 25–24 SRAM_U arbitration priority SRAMUAP Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_U array.
Page 362: Interrupt Status Register (Mcm_Iscr)
Memory map/register descriptions 17.2.4 Interrupt Status Register (MCM_ISCR) Address: E008_0000h base + 10h offset = E008_0010h Reserved Reset Reset MCM_ISCR field descriptions Field Description FPU input denormal interrupt enable FIDCE Disable interrupt Enable interrupt 30–29 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 363 Chapter 17 Miscellaneous Control Module (MCM) MCM_ISCR field descriptions (continued) Field Description FPU overflow interrupt enable FOFCE Disable interrupt Enable interrupt FPU divide-by-zero interrupt enable FDZCE Disable interrupt Enable interrupt FPU invalid operation interrupt enable FIOCE Disable interrupt Enable interrupt 23–16 This field is reserved.
Page 364 Memory map/register descriptions MCM_ISCR field descriptions (continued) Field Description FPU invalid operation interrupt status FIOC This read-only bit is a copy of the core’s FPSCR[IOC] bit and signals an illegal operation has been detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. No interrupt Interrupt occurred 7–5...
Page 365: Etb Counter Control Register (Mcm_Etbcc)
Chapter 17 Miscellaneous Control Module (MCM) 17.2.5 ETB Counter Control register (MCM_ETBCC) Address: E008_0000h base + 14h offset = E008_0014h Reset ITDIS RLRQ RSPT Reset MCM_ETBCC field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ITM-To-TPIU Disable ITDIS Disables the trace path from ITM to TPIU.
Page 366: Etb Reload Register (Mcm_Etbrl)
Memory map/register descriptions MCM_ETBCC field descriptions (continued) Field Description Generate an NMI when the ETB count expires Generate a debug halt when the ETB count expires Counter Enable CNTEN Enables the ETB counter. ETB counter disabled ETB counter enabled 17.2.6 ETB Reload register (MCM_ETBRL) Address: E008_0000h base + 18h offset = E008_0018h RELOAD Reset...
Page 367: Process Id Register (Mcm_Pid)
Chapter 17 Miscellaneous Control Module (MCM) 17.2.8 Process ID register (MCM_PID) This register drives the M0_PID and M1_PID values in the Memory Protection Unit(MPU). System software loads this register before passing control to a given user mode process. If the PID of the process does not match the value in this register, a bus error occurs.
Page 368: K22 Sub-Family Reference Manual, Rev. 4, November
Functional description 17.3.1.2 Normal interrupt The MCM's normal interrupt is generated if any of the following is true: • ISCR[ETBI] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires • The response to counter expiration is a normal interrupt, ETBCC[RSPT] = 01 •...
Page 369: Crossbar Switch (Axbs)
Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
Page 370: Memory Map / Register Definition
Memory Map / Register Definition 18.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and write- transfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode.
Page 371: Priority Registers Slave (Axbs_Prsn)
Chapter 18 Crossbar Switch (AXBS) AXBS memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_4710 Control Register (AXBS_CRS7) 0000_0000h 18.2.2/374 4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 0000_0000h 18.2.3/375 4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 0000_0000h 18.2.3/375 4000_4A00...
Page 372 Memory Map / Register Definition Reserved — Reset * Notes: • See the chip-specific crossbar information for the reset value of the PRSn registers. AXBS_PRSn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 30–28 This field is reserved.
Page 373 Chapter 18 Crossbar Switch (AXBS) AXBS_PRSn field descriptions (continued) Field Description 10–8 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. This master has level 1, or highest, priority when accessing the slave port. This master has level 2 priority when accessing the slave port.
Page 374: Control Register (Axbs_Crsn)
Memory Map / Register Definition 18.2.2 Control Register (AXBS_CRSn) These registers control several features of each slave port and must be accessed using 32- bit accesses. After CRSn[RO] is set, the PRSn can only be read; attempts to write to it have no effect and result in an error response.
Page 375: Master General Purpose Control Register (Axbs_Mgpcrn)
Chapter 18 Crossbar Switch (AXBS) AXBS_CRSn field descriptions (continued) Field Description Determines the slave port’s parking control. The low-power park feature results in an overall power savings if the slave port is not saturated. However, this forces an extra latency clock when any master tries to access the slave port while not in use because it is not parked on any master.
Page 376: Functional Description
Functional Description AXBS_MGPCRn field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 2–0 Arbitrates On Undefined Length Bursts AULB Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when the master is performing undefined length burst accesses.
Page 377: Register Coherency
Chapter 18 Crossbar Switch (AXBS) After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access. The master can also lose control of the slave port if another higher-priority master makes a request to the slave port.
Page 378 Functional Description 18.3.3.1 Arbitration during undefined length bursts Arbitration points during an undefined length burst are defined by the current master's MGPCR[AULB] field setting. When a defined length is imposed on the burst via the AULB bits, the undefined length burst is treated as a single or series of single back-to- back fixed-length burst accesses.
Page 379 Chapter 18 Crossbar Switch (AXBS) 18.3.3.2 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level in the priority registers (PRSn) . If two masters request access to the same slave port, the master with the highest priority in the selected priority register gains control over the slave port.
Page 380: Initialization/Application Information
Initialization/application information master becomes owner of the slave bus at the next transfer boundary, accounting for locked and fixed-length burst transfers. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port.
Page 381: Memory Protection Unit (Mpu)
Chapter 19 Memory Protection Unit (MPU) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The memory protection unit (MPU) provides hardware access control for all memory references generated in the device. 19.2 Overview The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and...
Page 382: Features
Overview Slave Port n Internal Address Phase Signals Peripheral Bus Access Region Evaluation Descriptor 0 Macro Access Region Evaluation Descriptor 1 Macro Access Region Evaluation Descriptor x Macro MPU_EARn MPU_EDRn Figure 19-1. MPU block diagram The hardware's two-dimensional connection matrix is clearly visible with the basic access evaluation macro shown as the replicated submodule block.
Page 383: Memory Map/Register Definition
Chapter 19 Memory Protection Unit (MPU) • Region sizes can vary from 32 bytes to 4 Gbytes • Two access control permissions defined in a single descriptor word • Masters 0–3: read, write, and execute attributes for supervisor and user accesses •...
Page 384 Memory map/register definition MPU memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_D000 Control/Error Status Register (MPU_CESR) 0081_5101h 19.3.1/386 4000_D010 Error Address Register, slave port n (MPU_EAR0) Undefined 19.3.2/387 4000_D014 Error Detail Register, slave port n (MPU_EDR0) Undefined 19.3.3/388 4000_D018 Error Address Register, slave port n (MPU_EAR1)
Page 385 Chapter 19 Memory Protection Unit (MPU) MPU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_D46C Region Descriptor n, Word 3 (MPU_RGD6_WORD3) See section 19.3.7/393 4000_D470 Region Descriptor n, Word 0 (MPU_RGD7_WORD0) 0000_0000h 19.3.4/389 4000_D474 Region Descriptor n, Word 1 (MPU_RGD7_WORD1)
Page 386: Control/Error Status Register (Mpu_Cesr)
Memory map/register definition MPU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Region Descriptor Alternate Access Control n 4000_D828 See section 19.3.8/394 (MPU_RGDAAC10) Region Descriptor Alternate Access Control n 4000_D82C See section 19.3.8/394 (MPU_RGDAAC11) 19.3.1 Control/Error Status Register (MPU_CESR)
Page 387: Error Address Register, Slave Port N (Mpu_Earn)
Chapter 19 Memory Protection Unit (MPU) MPU_CESR field descriptions (continued) Field Description 19–16 Hardware Revision Level Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. 15–12 Number Of Slave Ports Specifies the number of slave ports connected to the MPU.
Page 388: Error Detail Register, Slave Port N (Mpu_Edrn)
Memory map/register definition MPU_EARn field descriptions Field Description 31–0 Error Address EADDR Indicates the reference address from slave port n that generated the access error 19.3.3 Error Detail Register, slave port n (MPU_EDRn) When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in CESR[SPERR] is set.
Page 389: Region Descriptor N, Word 0 (Mpu_Rgdn_Word0)
Chapter 19 Memory Protection Unit (MPU) MPU_EDRn field descriptions (continued) Field Description 7–4 Error Master Number Indicates the bus master that generated the access error. 3–1 Error Attributes EATTR Indicates attribute information about the faulting reference. NOTE: All other encodings are reserved. User mode, instruction access User mode, data access Supervisor mode, instruction access...
Page 390: Region Descriptor N, Word 1 (Mpu_Rgdn_Word1)
Memory map/register definition 19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1) The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). Address: 4000_D000h base + 404h offset + (16d × i), where i=0d to 11d Reserved ENDADDR Reset...
Page 391 Chapter 19 Memory Protection Unit (MPU) • Write (w) refers to updating the referenced memory address using a store (data) instruction • Execute (x) refers to reading the referenced memory address using an instruction fetch Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]).
Page 392 Memory map/register definition MPU_RGDn_WORD2 field descriptions (continued) Field Description Bus master 5 reads terminate with an access error and the read is not performed Bus master 5 reads allowed Bus Master 5 Write Enable M5WE Bus master 5 writes terminate with an access error and the write is not performed Bus master 5 writes allowed Bus Master 4 Read Enable M4RE...
Page 393: Region Descriptor N, Word 3 (Mpu_Rgdn_Word3)
Chapter 19 Memory Protection Unit (MPU) MPU_RGDn_WORD2 field descriptions (continued) Field Description 8–6 Bus Master 1 User Mode Access Control M1UM See M3UM description. Bus Master 0 Process Identifier enable M0PE See M0PE description. 4–3 Bus Master 0 Supervisor Mode Access Control M0SM See M3SM description.
Page 394: Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
Memory map/register definition MPU_RGDn_WORD3 field descriptions (continued) Field Description 15–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Valid Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit. Region descriptor is invalid Region descriptor is valid 19.3.8 Region Descriptor Alternate Access Control n...
Page 395 Chapter 19 Memory Protection Unit (MPU) MPU_RGDAACn field descriptions (continued) Field Description Bus Master 7 Write Enable M7WE Bus master 7 writes terminate with an access error and the write is not performed Bus master 7 writes allowed Bus Master 6 Read Enable M6RE Bus master 6 reads terminate with an access error and the read is not performed Bus master 6 reads allowed...
Page 396: Functional Description
Functional description MPU_RGDAACn field descriptions (continued) Field Description See M3PE description. 16–15 Bus Master 2 Supervisor Mode Access Control M2SM See M3SM description. 14–12 Bus Master 2 User Mode Access Control M2UM See M3UM description. Bus Master 1 Process Identifier Enable M1PE See M3PE description.
Page 397 Chapter 19 Memory Protection Unit (MPU) RGDn start Address r,w,x ≥ ≤ error hit_b ≥ ≥ MPU_EDRn Access not allowed (no hit OR error) (hit AND error) Figure 19-80. MPU access evaluation macro 19.4.1.1 Hit determination To determine whether the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses.
Page 398: Putting It All Together And Error Terminations
Functional description 19.4.1.2 Privilege violation determination While the access evaluation macro is determining region hit, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. Using the master and supervisor/user mode signals, a set of effective permissions is generated from the appropriate fields in the region descriptor.
Page 399: Power Management
Chapter 19 Memory Protection Unit (MPU) 19.4.3 Power management Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize the power dissipation of an enabled MPU, invalidate unused region descriptors by clearing the associated RGDn_Word3[VLD] bits. 19.5 Initialization information At system startup, load the appropriate number of region descriptors, including setting RGDn_Word3[VLD].
Page 400 Application information • Detecting an access error—The current bus cycle is terminated with an error response and EARn and EDRn capture information on the faulting reference. The error-terminated bus cycle typically initiates an error response in the originating bus master. For example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt.
Page 401 Chapter 19 Memory Protection Unit (MPU) The space defined by RGD2 with no overlap is a private data and stack area that provides read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR of the two region descriptors.
Page 402 Application information K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 403: Peripheral Bridge (Aips-Lite)
Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge occupies 64 MB of the address space, which is divided into 4-KB peripheral slots.
Page 404: Functional Description
Functional description • Transfer attributes • Byte enables • Write data The peripheral bridge selects and captures read data from the peripheral interface and returns it to the crossbar switch. The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map.
Page 405: Direct Memory Access Multiplexer (Dmamux)
Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 21.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K22 Sub-Family Reference Manual, Rev.
Page 406: Features
Introduction DMA channel #0 DMAMUX Source #1 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 21-1. DMAMUX block diagram 21.1.2 Features The DMAMUX module provides these features: •...
Page 407: External Signal Description
Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
Page 408: Channel Configuration Register (Dmamux_Chcfgn)
Memory map/register definition DMAMUX memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_1009 Channel Configuration register (DMAMUX_CHCFG9) 21.3.1/408 4002_100A Channel Configuration register (DMAMUX_CHCFG10) 21.3.1/408 4002_100B Channel Configuration register (DMAMUX_CHCFG11) 21.3.1/408 4002_100C Channel Configuration register (DMAMUX_CHCFG12) 21.3.1/408 4002_100D Channel Configuration register (DMAMUX_CHCFG13) 21.3.1/408...
Page 409: Functional Description
Chapter 21 Direct Memory Access Multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions (continued) Field Description Triggering is disabled. If triggering is disabled and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled.
Page 410 Functional description Source #1 Source #2 Source #3 DMA channel #0 Trigger #1 Source #x DMA channel #m-1 Trigger #m Always #1 Always #y Figure 21-19. DMAMUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 411: Dma Channels With No Triggering Capability
Chapter 21 Direct Memory Access Multiplexer (DMAMUX) Peripheral request Trigger DMA request Figure 21-21. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •...
Page 412: Always-Enabled Dma Sources
Functional description 21.4.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling"...
Page 413: Initialization/Application Information
Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability.
Page 414: K22 Sub-Family Reference Manual, Rev. 4, November
Initialization/application information 2. Configure channel 1 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG1 (base address + 0x01). The following code example illustrates steps 1 and 4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */...
Page 415 Chapter 21 Direct Memory Access Multiplexer (DMAMUX) The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);...
Page 416 Initialization/application information In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);...
Page 417: Direct Memory Access Controller (Edma)
Chapter 22 Direct Memory Access Controller (eDMA) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor.
Page 418: Block Parts
Introduction eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 22-1. eDMA block diagram 22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
Page 419 Chapter 22 Direct Memory Access Controller (eDMA) Table 22-1. eDMA engine submodules Submodule Function Address path This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality.
Page 420: Features
Introduction 22.1.3 Features The eDMA is a highly programmable data-transfer engine optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the data packet itself.
Page 421: Modes Of Operation
Chapter 22 Direct Memory Access Controller (eDMA) • Support for complex data structures • Support to cancel transfers via software In the discussion of this module, n is used to reference the channel number. 22.2 Modes of operation The eDMA operates in the following modes: Table 22-3.
Page 422 Memory map/register definition Here is the TCD structure: TCD Structure DMA Basics: • One DMA engine has a number of channels to react to DMA requests • Each channel has its own TCD Word Offset SADDR 0x1000 0x1004 SMOD SSIZE DMOD DSIZE SOFF...
Page 423 Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) (always 22.3.6/443 reads 0) 4000_801A Clear Enable Request Register (DMA_CERQ) (always 22.3.7/444 reads 0)
Page 424 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) Undefined 22.3.19/459 TCD Minor Byte Count (Minor Loop Disabled) 4000_9008 Undefined 22.3.20/460 (DMA_TCD0_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9008 Undefined 22.3.21/460...
Page 425 Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_903E (Channel Linking Enabled) Undefined 22.3.30/470 (DMA_TCD1_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_903E Undefined 22.3.31/471...
Page 426 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Destination Address Offset 4000_9074 Undefined 22.3.25/464 (DMA_TCD3_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9076 Undefined 22.3.26/464 Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 4000_9076...
Page 427 Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_90A8 Undefined 22.3.21/460 Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_90A8 Undefined 22.3.22/462...
Page 428 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_90DE Undefined 22.3.31/471 (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) Undefined 22.3.17/458 4000_90E4...
Page 429 Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9116 DMA_TCD8_CITER_ELINKNO Undefined 22.3.27/466 TCD Last Destination Address Adjustment/Scatter Gather 4000_9118 Undefined 22.3.28/467 Address (DMA_TCD8_DLASTSGA) 4000_911C TCD Control and Status (DMA_TCD8_CSR) Undefined 22.3.29/467 TCD Beginning Minor Loop Link, Major Loop Count...
Page 430 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Source Address Adjustment 4000_914C Undefined 22.3.23/463 (DMA_TCD10_SLAST) 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) Undefined 22.3.24/463 TCD Signed Destination Address Offset 4000_9154 Undefined 22.3.25/464...
Page 431 Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9180 TCD Source Address (DMA_TCD12_SADDR) Undefined 22.3.17/458 4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) Undefined 22.3.18/458 4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) Undefined...
Page 432 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Destination Address Adjustment/Scatter Gather 4000_91B8 Undefined 22.3.28/467 Address (DMA_TCD13_DLASTSGA) 4000_91BC TCD Control and Status (DMA_TCD13_CSR) Undefined 22.3.29/467 TCD Beginning Minor Loop Link, Major Loop Count 4000_91BE (Channel Linking Enabled) Undefined...
Page 433: Control Register (Dma_Cr)
Chapter 22 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_91E8 Undefined 22.3.22/462 Enabled) (DMA_TCD15_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_91EC Undefined 22.3.23/463...
Page 434 Memory map/register definition complete, the minor loop offset is ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify the minor loop offset should be applied to the source address (TCDn_SADDR) upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop...
Page 435 Chapter 22 Direct Memory Access Controller (eDMA) DMA_CR field descriptions (continued) Field Description Normal operation Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence.
Page 436: Error Status Register (Dma_Es)
Memory map/register definition 22.3.2 Error Status Register (DMA_ES) The ES provides information concerning the last recorded channel error. Channel errors can be caused by: • A configuration error, that is: • An illegal setting in the transfer-control descriptor, or • An illegal priority register setting in fixed-arbitration •...
Page 437 Chapter 22 Direct Memory Access Controller (eDMA) DMA_ES field descriptions (continued) Field Description 11–8 Error Channel Number or Canceled Channel Number ERRCHN The channel number of the last recorded error (excluding CPE errors) or last recorded error canceled transfer. Source Address Error No source address configuration error.
Page 438: Enable Request Register (Dma_Erq)
Memory map/register definition 22.3.3 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 16 implemented channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQ.
Page 439 Chapter 22 Direct Memory Access Controller (eDMA) DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 12 ERQ12 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 11 ERQ11 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled...
Page 440: Enable Error Interrupt Register (Dma_Eei)
Memory map/register definition DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 0 ERQ0 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 22.3.4 Enable Error Interrupt Register (DMA_EEI) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel.
Page 441 Chapter 22 Direct Memory Access Controller (eDMA) DMA_EEI field descriptions (continued) Field Description Enable Error Interrupt 13 EEI13 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 12 EEI12 The error signal for corresponding channel does not generate an error interrupt...
Page 442: Clear Enable Error Interrupt Register (Dma_Ceei)
Memory map/register definition DMA_EEI field descriptions (continued) Field Description Enable Error Interrupt 1 EEI1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 0 EEI0 The error signal for corresponding channel does not generate an error interrupt...
Page 443: Set Enable Error Interrupt Register (Dma_Seei)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set.
Page 444: Clear Enable Request Register (Dma_Cerq)
Memory map/register definition 22.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared.
Page 445: Set Enable Request Register (Dma_Serq)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set.
Page 446: Clear Done Status Bit Register (Dma_Cdne)
Memory map/register definition 22.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared.
Page 447: Set Start Bit Register (Dma_Ssrt)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set.
Page 448: Clear Error Register (Dma_Cerr)
Memory map/register definition 22.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared.
Page 449: Clear Interrupt Request Register (Dma_Cint)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared.
Page 450: Interrupt Request Register (Dma_Int)
Memory map/register definition 22.3.13 Interrupt Request Register (DMA_INT) The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion.
Page 451 Chapter 22 Direct Memory Access Controller (eDMA) DMA_INT field descriptions (continued) Field Description Interrupt Request 15 INT15 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 14 INT14 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 13 INT13...
Page 452: Error Register (Dma_Err)
Memory map/register definition DMA_INT field descriptions (continued) Field Description Interrupt Request 3 INT3 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 2 INT2 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 1 INT1...
Page 453 Chapter 22 Direct Memory Access Controller (eDMA) Address: 4000_8000h base + 2Ch offset = 4000_802Ch Reset Reset DMA_ERR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Error In Channel 15 ERR15 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred...
Page 454 Memory map/register definition DMA_ERR field descriptions (continued) Field Description Error In Channel 9 ERR9 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 8 ERR8 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 7 ERR7...
Page 455: Hardware Request Status Register (Dma_Hrs)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.15 Hardware Request Status Register (DMA_HRS) The HRS register provides a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA’s arbitration logic.
Page 456 Memory map/register definition DMA_HRS field descriptions (continued) Field Description Hardware Request Status Channel 12 HRS12 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present Hardware Request Status Channel 11 HRS11 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present...
Page 457: Channel N Priority Register (Dma_Dchprin)
Chapter 22 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions (continued) Field Description Hardware Request Status Channel 0 HRS0 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present 22.3.16 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel .
Page 458: Tcd Source Address (Dma_Tcdn_Saddr)
Memory map/register definition 22.3.17 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d × i), where i=0d to 15d SADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 459: Tcd Transfer Attributes (Dma_Tcdn_Attr)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d × i), where i=0d to 15d Read SMOD SSIZE DMOD DSIZE Write Reset * Notes: • x = Undefined at reset. DMA_TCDn_ATTR field descriptions Field Description...
Page 460: Tcd Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
Memory map/register definition 22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used.
Page 461: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 22 Direct Memory Access Controller (eDMA) TCD word 2 is defined as follows if: • Minor loop mapping is enabled (CR[EMLM] = 1) and • SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set, then refer to the TCD_NBYTES_MLOFFYES register description.
Page 462: Tcd Signed Minor Loop Offset (Minor Loop And Offset Enabled)
Memory map/register definition 22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used.
Page 463: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
Chapter 22 Direct Memory Access Controller (eDMA) DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR 29–10 If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or MLOFF destination address to form the next-state value after the minor loop completes.
Page 464: Tcd Signed Destination Address Offset (Dma_Tcdn_Doff)
Memory map/register definition DMA_TCDn_DADDR field descriptions Field Description 31–0 Destination Address DADDR Memory address pointing to the destination data. 22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d × i), where i=0d to 15d Read DOFF Write...
Page 465 Chapter 22 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKYES field descriptions Field Description Enable channel-to-channel linking on minor-loop complete ELINK As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 466: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Memory map/register definition 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO) If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 15d Read ELINK CITER...
Page 467: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
Chapter 22 Direct Memory Access Controller (eDMA) 22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) Address: 4000_8000h base + 1018h offset + (32d × i), where i=0d to 15d DLASTSGA x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 468 Memory map/register definition DMA_TCDn_CSR field descriptions Field Description 15–14 Bandwidth Control Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.
Page 469 Chapter 22 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description The current channel’s TCD is normal format. The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. Disable Request DREQ If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current...
Page 470: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
Memory map/register definition 22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES) If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d × i), where i=0d to 15d Read ELINK LINKCH...
Page 471: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Chapter 22 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field.
Page 472: Functional Description
Functional description DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field.
Page 473 Chapter 22 Direct Memory Access Controller (eDMA) This example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration.
Page 474 Functional description The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write.
Page 475: Error Reporting And Handling
Chapter 22 Direct Memory Access Controller (eDMA) 22.4.2 Error reporting and handling Channel errors are reported in the Error Status register (DMAx_ES) and can be caused • A configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in Fixed-Arbitration mode, or •...
Page 476: Channel Preemption
Functional description data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer request is recognized, the DMA engine stops processing the channel.
Page 477: Performance
Chapter 22 Direct Memory Access Controller (eDMA) A channel’s ability to preempt another channel can be disabled by setting DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s ECP setting.
Page 478 Functional description Table 22-292. eDMA peak transfer rates (Mbytes/sec) Internal SRAM-to- Internal SRAM-to-32b 32b internal peripheral bus- System Speed, Width to-Internal SRAM Internal SRAM internal peripheral bus 66.7 MHz, 32b 133.3 66.7 53.3 83.3 MHz, 32b 166.7 83.3 66.7 100.0 MHz, 32b 200.0 100.0 80.0...
Page 479 Chapter 22 Direct Memory Access Controller (eDMA) Table 22-293. Hardware service request process (continued) Cycle Description With internal peripheral With SRAM read and bus read and internal internal peripheral bus SRAM write write 5–6 The first two parts of the activated channel's TCD is read from the local memory.
Page 480 Functional description A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 22-295. Peak request formula operands Operand Description PEAKreq Peak request rate...
Page 481: Initialization/Application Information
Chapter 22 Direct Memory Access Controller (eDMA) • 11 cycles for a software, that is, a TCDn_CSR[START] bit, request • 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals.
Page 482 Initialization/application information After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module.
Page 483: Programming Errors
Chapter 22 Direct Memory Access Controller (eDMA) Current major loop iteration Source or destination memory count (CITER) DMA request DMA request DMA request Figure 22-292. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. xADDR: (Starting address) xSIZE: (size of one Minor loop...
Page 484: Arbitration Mode Considerations
Initialization/application information For all error types other than channel priority error, the channel number causing the error is recorded in the Error Status register (DMAx_ES). If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again.
Page 485 Chapter 22 Direct Memory Access Controller (eDMA) programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCDn_CITER = TCDn_BITER = 1 TCDn_NBYTES = 16 TCDn_SADDR = 0x1000...
Page 486 Initialization/application information 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. 22.5.4.2 Multiple requests The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example.
Page 487 Chapter 22 Direct Memory Access Controller (eDMA) g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1.
Page 488: Monitoring Transfer Descriptor Status
Initialization/application information 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 22.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation.
Page 489 Chapter 22 Direct Memory Access Controller (eDMA) The TCD status bits execute the following sequence for a software activated channel: TCDn_CSR bits Stage State START ACTIVE DONE Channel service request via software Channel is executing Channel has completed the minor loop and is idle Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the TCDn_CITER field and test for a...
Page 490: Channel Linking
Initialization/application information 22.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined.
Page 491: Dynamic Programming
Chapter 22 Direct Memory Access Controller (eDMA) When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count.
Page 492 Initialization/application information 22.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed.
Page 493 Chapter 22 Direct Memory Access Controller (eDMA) is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. Two methods for this coherency model are shown in the following subsections. Method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read.
Page 494 Initialization/application information If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). 22.5.7.3.2 Method 2 (channel using major loop channel linking) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request.
Page 495: External Watchdog Monitor (Ewm)
Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
Page 496: Modes Of Operation
Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles.
Page 497: Block Diagram
Chapter 23 External Watchdog Monitor (EWM) 23.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 23.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. •...
Page 498: Ewm Signal Descriptions
EWM Signal Descriptions 23.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 23-1. EWM Signal Descriptions Signal Description EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low.
Page 499: Service Register (Ewm_Serv)
Chapter 23 External Watchdog Monitor (EWM) EWM_CTRL field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Interrupt Enable. INTEN This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0.
Page 500: Compare High Register (Ewm_Cmph)
Memory Map/Register Definition NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: 4006_1000h base + 2h offset = 4006_1002h Read COMPAREL Write Reset EWM_CMPL field descriptions Field Description 7–0...
Page 501: Functional Description
Chapter 23 External Watchdog Monitor (EWM) 23.4 Functional Description The following sections describe functional details of the EWM module. 23.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance.
Page 502: The Ewm_In Signal
Functional Description 23.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit.
Page 503: Ewm Refresh Mechanism
Chapter 23 External Watchdog Monitor (EWM) • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted.
Page 504 Functional Description K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 505: Watchdog Timer (Wdog)
Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences.
Page 506 Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. •...
Page 507: Functional Overview
Chapter 24 Watchdog Timer (WDOG) 24.3 Functional overview WDOG Disable Control/Configuration Unlock Sequence bit changes N bus clk cycles after 2 Writes of data within K bus clock unlocking cycles of each other Refresh Sequence 2 writes of data within K 0xC520 bus clock cycles of each N bus clk cycles...
Page 508: Unlocking And Updating The Watchdog
Functional overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application.
Page 509: Watchdog Configuration Time (Wct)
Chapter 24 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed.
Page 510: Refreshing The Watchdog
Functional overview Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. 24.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog.
Page 511: Debug Modes Of Operation
Chapter 24 Watchdog Timer (WDOG) time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 24.3.6 Debug modes of operation You can program the watchdog to disable in debug modes through DBG_EN in the watchdog control register.
Page 512: Quick Test
Testing the watchdog Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts more details. To run a particular test: 1.
Page 513: Backup Reset Generator
Chapter 24 Watchdog Timer (WDOG) Reset Value (Hardwired) Modulus Register (Time-out Value) Byte 3 Byte 4 Byte 2 Byte 1 WDOG Reset WDOG Equality Comparison Mod = = Timer? Test 32-bit Timer Byte Byte Byte Byte Stage 1 Stage 2 Stage 3 Stage 4 Nth Stage Overflow Enables N + 1th Stage...
Page 514: Generated Resets And Interrupts
Generated resets and interrupts 24.6 Generated resets and interrupts The watchdog generates a reset in the following events, also referred to as exceptions: • A watchdog time-out • Failure to unlock the watchdog within WCT time after system reset deassertion •...
Page 515: Watchdog Status And Control Register High (Wdog_Stctrlh)
Chapter 24 Watchdog Timer (WDOG) WDOG memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Watchdog Status and Control Register High 4005_2000 01D3h 24.7.1/515 (WDOG_STCTRLH) Watchdog Status and Control Register Low 4005_2002 0001h 24.7.2/517 (WDOG_STCTRLL) 4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH)
Page 516 Memory map and register definition WDOG_STCTRLH field descriptions (continued) Field Description Byte 0 selected Byte 1 selected Byte 2 selected Byte 3 selected Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. TESTSEL Quick test.
Page 517: Watchdog Status And Control Register Low (Wdog_Stctrll)
Chapter 24 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset WDOGEN state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
Page 518: Watchdog Time-Out Value Register Low (Wdog_Tovall)
Memory map and register definition 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain.
Page 519: Watchdog Window Register Low (Wdog_Winl)
Chapter 24 Watchdog Timer (WDOG) 24.7.6 Watchdog Window Register Low (WDOG_WINL) NOTE You must set the Window Register value lower than the Time- out Value Register. Address: 4005_2000h base + Ah offset = 4005_200Ah Read WINLOW Write Reset WDOG_WINL field descriptions Field Description 15–0...
Page 520: Watchdog Timer Output Register High (Wdog_Tmrouth)
Memory map and register definition WDOG_UNLOCK field descriptions Field Description 15–0 Writing the unlock sequence values to this register to makes the watchdog write-once registers writable WDOGUNLOCK again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a window equal in length to the WCT within which you can update the registers.
Page 521: Watchdog Reset Count Register (Wdog_Rstcnt)
Chapter 24 Watchdog Timer (WDOG) 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT) Address: 4005_2000h base + 14h offset = 4005_2014h Read RSTCNT Write Reset WDOG_RSTCNT field descriptions Field Description 15–0 Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing RSTCNT 1 to the bit to be cleared enables you to clear the contents of this register.
Page 522: Refresh And Unlock Operations With 8-Bit Access
Watchdog operation with 8-bit access 24.8.2 Refresh and unlock operations with 8-bit access One exception condition that generates a reset to the system is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers.
Page 523: Restrictions On Watchdog Operation
Chapter 24 Watchdog Timer (WDOG) It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. The difference for 8-bit accesses is that the criterion for detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections Refreshing the Watchdog.
Page 524 Restrictions on watchdog operation • You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock. •...
Page 525: Multipurpose Clock Generator (Mcg)
Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL).
Page 526 Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. •...
Page 527 Chapter 25 Multipurpose Clock Generator (MCG) • External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes • Lock detector with interrupt request capability for use with the PLL •...
Page 528 Introduction Crystal Oscillator Oscillator External Reference Clock CLKS OSCINIT0 PLLCLKEN0 MCG Crystal Oscillator Enable Detect EREFS0 IREFS HGO0 PLLS ATMS RANGE0 OSCSEL STOP IREFSTEN Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM IRCS Internal CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock FCTRIM...
Page 529: Modes Of Operation
Chapter 25 Multipurpose Clock Generator (MCG) 25.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 25.2 External Signal Description There are no MCG signals that connect off chip. 25.3 Memory Map/Register Definition This section includes the memory map and register definition.
Page 530: Mcg Control 1 Register (Mcg_C1)
Memory Map/Register Definition 25.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 —...
Page 531: Mcg Control 2 Register (Mcg_C2)
Chapter 25 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable IREFSTEN Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
Page 532: Mcg Control 3 Register (Mcg_C3)
Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode.
Page 533: Mcg Control 4 Register (Mcg_C4)
Chapter 25 Multipurpose Clock Generator (MCG) 25.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset * Notes: • x = Undefined at reset.
Page 534: Mcg Control 5 Register (Mcg_C5)
Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description Encoding 1 — Mid range. Encoding 2 — Mid-high range. Encoding 3 — High range. 4–1 Fast Internal Reference Clock Trim Setting FCTRIM FCTRIM controls the fast internal reference clock frequency by controlling the fast internal reference clock period.
Page 535: Mcg Control 6 Register (Mcg_C6)
Chapter 25 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1.
Page 536 Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. No interrupt request is generated on loss of lock. Generate an interrupt request on loss of lock.
Page 537: Mcg Status Register (Mcg_S)
Chapter 25 Multipurpose Clock Generator (MCG) 25.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Read LOLS LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST Write Reset MCG_S field descriptions Field Description Loss of Lock Status LOLS This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D .
Page 538: Mcg Status And Control Register (Mcg_Sc)
Memory Map/Register Definition MCG_S field descriptions (continued) Field Description 3–2 Clock Mode Status CLKST These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. Encoding 0 —...
Page 539 Chapter 25 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description Automatic Trim Machine Select ATMS Selects the IRCS clock for Auto Trim Test. 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Automatic Trim Machine Fail Flag ATMF Fail flag for the Automatic Trim Machine (ATM).
Page 540: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Memory Map/Register Definition 25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Read ATCVH Write Reset MCG_ATCVH field descriptions Field Description 7–0 ATM Compare Value High ATCVH Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion.
Page 541: Mcg Control 8 Register (Mcg_C8)
Chapter 25 Multipurpose Clock Generator (MCG) MCG_C7 field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–1 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. MCG OSC Clock Select OSCSEL Selects the MCG FLL external reference clock...
Page 542: Functional Description
Functional Description MCG_C8 field descriptions (continued) Field Description External clock monitor is disabled for RTC clock. External clock monitor is enabled for RTC clock. 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. RTC Loss of Clock Status LOCS1 This bit indicates when a loss of clock has occurred.
Page 543 Chapter 25 Multipurpose Clock Generator (MCG) NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10. •...
Page 544 Functional Description Table 25-16. MCG modes of operation (continued) Mode Description FLL Engaged External FLL engaged external (FEE) mode is entered when all the following conditions occur: (FEE) • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 •...
Page 545 Chapter 25 Multipurpose Clock Generator (MCG) Table 25-16. MCG modes of operation (continued) Mode Description PLL Engaged External PLL Engaged External (PEE) mode is entered when all the following conditions occur: (PEE) • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 •...
Page 546 Functional Description Table 25-16. MCG modes of operation (continued) Mode Description Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery.
Page 547: Low Power Bit Usage
Chapter 25 Multipurpose Clock Generator (MCG) The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1. If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO range within three clocks of the selected DCO clock.
Page 548: External Reference Clock
Functional Description Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. 25.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range.
Page 549: Mcg Pll Clock
Chapter 25 Multipurpose Clock Generator (MCG) 25.4.6 MCG PLL clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set.
Page 550: Initialization / Application Information
Initialization / Application information Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV •...
Page 551 Chapter 25 Multipurpose Clock Generator (MCG) 2. Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source.
Page 552: Using A 32.768 Khz Reference
Initialization / Application information • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz.
Page 553: Mcg Mode Switching
Chapter 25 Multipurpose Clock Generator (MCG) 25.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range.
Page 554 Initialization / Application information Table 25-17. MCGOUTCLK Frequency Calculation Options (continued) Clock Mode Note MCGOUTCLK FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast PEE (PLL engaged external) (OSCCLK / PLL_R) * M OSCCLK / PLL_R must be in the...
Page 555 Chapter 25 Multipurpose Clock Generator (MCG) • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator.
Page 556 Initialization / Application information 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode.
Page 557 Chapter 25 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C BLPE MODE ? (S[LP]=1) C1 = 0x90 C2 = 0x1C (S[LP]=0) CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? CHECK S[IREFST] = 0? CHECK S[LOCK] = 1? CHECK S[CLKST] = %10?
Page 558 Initialization / Application information 25.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.
Page 559 Chapter 25 Multipurpose Clock Generator (MCG) • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source.
Page 560 Initialization / Application information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? CHECK S[CLKST] = %10 ? C1 = 0x54 ENTER CHECK BLPE MODE ? S[IREFST] = 0? C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 C2 = 0x02 BLPE MODE ?
Page 561 Chapter 25 Multipurpose Clock Generator (MCG) 25.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency.
Page 562 Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK S[IREFST] = 0? C2 = 0x00 C2 = 0x1C CHECK...
Page 563: Oscillator (Osc)
Chapter 26 Oscillator (OSC) 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 26.2 Features and Modes Key features of the module are: •...
Page 564: Block Diagram
Block Diagram 26.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode.
Page 565: External Crystal / Resonator Connections
Chapter 26 Oscillator (OSC) Table 26-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 26.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
Page 566: External Clock Connections
External Clock Connections XTAL EXTAL Crystal or Resonator Figure 26-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. XTAL EXTAL Crystal or Resonator Figure 26-4.
Page 567: Memory Map/Register Definitions
Chapter 26 Oscillator (OSC) XTAL EXTAL Clock Input Figure 26-5. External Clock Connections 26.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 26.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/...
Page 568: Functional Description
Functional Description OSC_CR field descriptions Field Description External Reference Enable ERCLKEN Enables external reference clock (OSCERCLK). External reference clock is inactive. External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters...
Page 569: Osc Module States
Chapter 26 Oscillator (OSC) 26.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested &&...
Page 570: Osc Module Modes
Functional Description 26.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 571 Chapter 26 Oscillator (OSC) Table 26-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain (1 kHz) up to f (32.768 kHz) osc_lo osc_lo High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power High-frequency mode2, high-gain (8 MHz) up to f (32 MHz) osc_hi_2...
Page 572: Counter
Reset 26.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
Page 573: Low Power Modes Operation
Chapter 26 Oscillator (OSC) 26.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
Page 574 Interrupts K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 575: Rtc Oscillator (Osc32K)
Chapter 27 RTC Oscillator (OSC32K) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 27.1.1 Features and Modes The key features of the RTC oscillator are as follows: •...
Page 576: Rtc Signal Descriptions
RTC Signal Descriptions control Amplitude clk out for RTC EXTAL32 detector XTAL32 Figure 27-1. RTC Oscillator Block Diagram 27.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins.
Page 577: External Crystal Connections
Chapter 27 RTC Oscillator (OSC32K) 27.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 EXTAL32 Crystal or Resonator Figure 27-2. Crystal Connections 27.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers.
Page 578: Reset Overview
Reset Overview 27.6 Reset Overview There is no reset state associated with the RTC oscillator. 27.7 Interrupts The RTC oscillator does not generate any interrupts. K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 579: Flash Memory Controller (Fmc)
Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM.
Page 580: Features
Modes of operation 28.1.2 Features The FMC's features include: • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM.
Page 581: Memory Map And Register Descriptions
Chapter 28 Flash Memory Controller (FMC) 28.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM).
Page 582 Memory map and register descriptions Table 28-3. Program visible cache registers Cache Based at Contents of 32-bit read Nomenclature Nomenclature example storage offset 100h 12'h0, tag[19:6], 5'h0, valid In TAGVDWxSy, x denotes the way TAGVDW2S0 is the 14-bit tag and y denotes the set. and 1-bit valid for cache entry way 2, set 0.
Page 583 Chapter 28 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Cache Data Storage (lowermost word) 28.4.11/ 4001_F20C 0000_0000h (FMC_DATAW0S0LM) Cache Data Storage (uppermost word) 4001_F210 0000_0000h 28.4.8/598 (FMC_DATAW0S1UM) Cache Data Storage (mid-upper word) 4001_F214...
Page 584 Memory map and register descriptions FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Cache Data Storage (mid-upper word) 28.4.13/ 4001_F264 0000_0000h (FMC_DATAW1S2MU) Cache Data Storage (mid-lower word) 28.4.14/ 4001_F268 0000_0000h (FMC_DATAW1S2ML) Cache Data Storage (lowermost word) 28.4.15/ 4001_F26C...
Page 585 Chapter 28 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Cache Data Storage (lowermost word) 28.4.19/ 4001_F2BC 0000_0000h (FMC_DATAW2S3LM) Cache Data Storage (uppermost word) 28.4.20/ 4001_F2C0 0000_0000h (FMC_DATAW3S0UM) Cache Data Storage (mid-upper word) 28.4.21/...
Page 586: Flash Access Protection Register (Fmc_Pfapr)
Memory map and register descriptions 28.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reset M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset FMC_PFAPR field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 587 Chapter 28 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field Description Master 3 Prefetch Disable M3PFD These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled.
Page 588 Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master 9–8 Master 4 Access Protection M4AP[1:0]...
Page 589: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
Chapter 28 Flash Memory Controller (FMC) 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h B0RWSC[3:0] B0MW[1:0] CLCK_WAY[3:0] S_B_ CINV_WAY[3:0] Reset CRC[2:0] Reset FMC_PFB0CR field descriptions Field Description 31–28 Bank 0 Read Wait State Control B0RWSC[3:0] This read-only field defines the number of wait states required to access the bank 0 flash memory.
Page 590 Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared.
Page 591 Chapter 28 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description Do not cache instruction fetches. Cache instruction fetches. Bank 0 Data Prefetch Enable B0DPE This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. Do not prefetch in response to data references.
Page 592: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
Memory map and register descriptions 28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR) This register has a format similar to that for PFB0CR, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. Address: 4001_F000h base + 8h offset = 4001_F008h B1RWSC[3:0] B1MW[1:0] Reset...
Page 593 Chapter 28 Flash Memory Controller (FMC) FMC_PFB1CR field descriptions (continued) Field Description 32 bits 64 bits 128 bits Reserved This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 594: Cache Tag Storage (Fmc_Tagvdw0Sn)
Memory map and register descriptions 28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn) The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 595: Cache Tag Storage (Fmc_Tagvdw1Sn)
Chapter 28 Flash Memory Controller (FMC) 28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 596: Cache Tag Storage (Fmc_Tagvdw2Sn)
Memory map and register descriptions 28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 597: Cache Tag Storage (Fmc_Tagvdw3Sn)
Chapter 28 Flash Memory Controller (FMC) 28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The 128-entry cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 598: Cache Data Storage (Uppermost Word) (Fmc_Dataw0Snum)
Memory map and register descriptions 28.4.8 Cache Data Storage (uppermost word) (FMC_DATAW0SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 599: Cache Data Storage (Mid-Lower Word) (Fmc_Dataw0Snml)
Chapter 28 Flash Memory Controller (FMC) 28.4.10 Cache Data Storage (mid-lower word) (FMC_DATAW0SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 600: Cache Data Storage (Uppermost Word) (Fmc_Dataw1Snum)
Memory map and register descriptions 28.4.12 Cache Data Storage (uppermost word) (FMC_DATAW1SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 601: Cache Data Storage (Mid-Lower Word) (Fmc_Dataw1Snml)
Chapter 28 Flash Memory Controller (FMC) 28.4.14 Cache Data Storage (mid-lower word) (FMC_DATAW1SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 602: Cache Data Storage (Uppermost Word) (Fmc_Dataw2Snum)
Memory map and register descriptions 28.4.16 Cache Data Storage (uppermost word) (FMC_DATAW2SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 603: Cache Data Storage (Mid-Lower Word) (Fmc_Dataw2Snml)
Chapter 28 Flash Memory Controller (FMC) 28.4.18 Cache Data Storage (mid-lower word) (FMC_DATAW2SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 604: Cache Data Storage (Uppermost Word) (Fmc_Dataw3Snum)
Memory map and register descriptions 28.4.20 Cache Data Storage (uppermost word) (FMC_DATAW3SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 605: Cache Data Storage (Mid-Lower Word) (Fmc_Dataw3Snml)
Chapter 28 Flash Memory Controller (FMC) 28.4.22 Cache Data Storage (mid-lower word) (FMC_DATAW3SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 606: Functional Description
Functional description 28.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory and FlexMemory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times.
Page 607: Wait States
Chapter 28 Flash Memory Controller (FMC) • LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and • LRU with ways [0-2] for instruction fetches and way [3] for data fetches. As an application example: if both instruction fetches and data references are accessing bank 0, control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer.
Page 608: Speculative Reads
Functional description All wait states and synchronization delays are handled automatically by the Flash Memory Controller. No direct user configuration is required or even allowed to set up the flash wait states. 28.5.4 Speculative reads The FMC has a single buffer that reads ahead to the next word in the flash memory if there is an idle cycle.
Page 609: Initialization And Application Information
Chapter 28 Flash Memory Controller (FMC) 28.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. The FMC has no visibility into flash memory erase and program cycles because the Flash Memory module manages them directly.
Page 610 Initialization and application information K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 611: Flash Memory Module (Ftfe)
Chapter 29 Flash Memory Module (FTFE) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The FTFE module includes the following accessible memory regions: • Program flash memory for vector space and code store •...
Page 612: Features
Introduction The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved.
Page 613 Chapter 29 Flash Memory Module (FTFE) • Automated, built-in program and erase algorithms with verify • Section programming for faster bulk programming times • Read access to the data flash block possible while programming or erasing data in the program flash block 29.1.1.3 Programming Acceleration RAM features •...
Page 614: Block Diagram
Introduction • Optional interrupt generation upon flash command completion • Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 29.1.2 Block diagram The block diagram of the FTFE module is shown in the following figure. For devices with FlexNVM feature: Program flash Interrupt Program flash...
Page 615: Glossary
Chapter 29 Flash Memory Module (FTFE) Interrupt Program flash Status Register registers access Memory Program flash controller To MCU's Control flash controller registers Programming acceleration Figure 29-2. FTFE block diagram 29.1.3 Glossary Command write sequence — A series of MCU writes to the Flash FCCOB register group that initiates and controls the execution of Flash algorithms that are built into the FTFE module.
Page 616 Introduction EEPROM backup data memory — Partitioned from the FlexNVM block, EEPROM backup data memory provides nonvolatile storage for the EEPROM filing system representing data written to the FlexRAM requiring highest endurance. EEPROM backup data sector — The EEPROM backup data sector contains one EEPROM header and up to 255 EEPROM backup data records, which are used by the EEPROM filing system.
Page 617: External Signal Description
Chapter 29 Flash Memory Module (FTFE) Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. Word — 16 bits of data with an aligned word having byte-address[0] = 0. Program flash —...
Page 618: Program Flash 0 Ifr Map
Memory map and registers 29.3.1 Flash configuration field description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFE module. Flash Configuration Field Byte Size (Bytes) Field Description...
Page 619: Data Flash 0 Ifr Map
Chapter 29 Flash Memory Module (FTFE) 29.3.2.1 Program Once field The Program Once field in the program flash 0 IFR provides 64 bytes of user data storage separate from the program flash 0 main array. The user can program the Program Once field one time only as there is no program flash IFR erase mechanism available to the user.
Page 620 Memory map and registers Table 29-2. EEPROM Data Set Size Field Description Field Description This read-only bitfield is reserved and must always be written as one. Reserved EEPROM Split Factor — Determines the relative sizes of the two EEPROM subsystems. Each subsystem is allocated half of the available EEPROM-backup as defined by DEPART.
Page 621: Register Descriptions
Chapter 29 Flash Memory Module (FTFE) Table 29-3. FlexNVM partition code Data Flash IFR: 0x03FC DEPART = Unimplemented or Reserved Table 29-4. FlexNVM partition code field description Field Description This read-only bitfield is reserved and must always be written as one. Reserved FlexNVM Partition Code —...
Page 622 Memory map and registers sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1).
Page 623 Chapter 29 Flash Memory Module (FTFE) FTFE memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 29.34.6/ 4002_0013 Program Flash Protection Registers (FTFE_FPROT0) Undefined 29.34.7/ 4002_0016 EEPROM Protection Register (FTFE_FEPROT) Undefined 29.34.8/ 4002_0017 Data Flash Protection Register (FTFE_FDPROT) Undefined 29.34.1 Flash Status Register (FTFE_FSTAT)
Page 624 Memory map and registers FTFE_FSTAT field descriptions (continued) Field Description FTFE Read Collision Error Flag RDCOLERR The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE resource that was being manipulated by an FTFE command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic.
Page 625 Chapter 29 Flash Memory Module (FTFE) Address: 4002_0000h base + 1h offset = 4002_0001h Read ERSAREQ SWAP PFLSH RAMRDY EEERDY CCIE RDCOLLIE ERSSUSP Write Reset FTFE_FCNFG field descriptions Field Description Command Complete Interrupt Enable CCIE The CCIE bit controls interrupt generation when an FTFE command completes. Command complete interrupt disabled Command complete interrupt enabled.
Page 626 Memory map and registers FTFE_FCNFG field descriptions (continued) Field Description For devices with FlexNVM: Logical program flash 0 block is located at relative address 0x0000 For devices with program flash only: Logical program flash 0 block is located at relative address 0x0000 For devices with FlexNVM: Reserved For devices with program flash only: Logical program flash 1 block is located at relative address...
Page 627 Chapter 29 Flash Memory Module (FTFE) 29.34.3 Flash Security Register (FTFE_FSEC) This read-only register holds all bits associated with the security of the MCU and FTFE module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory.
Page 628 Memory map and registers FTFE_FSEC field descriptions (continued) Field Description Freescale factory access granted Freescale factory access denied Freescale factory access denied Freescale factory access granted 1–0 Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to FTFE module resources.
Page 629 Chapter 29 Flash Memory Module (FTFE) 29.34.5 Flash Common Command Object Registers (FTFE_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB.
Page 630 Memory map and registers FTFE_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] Data Byte 6 Data Byte 7 1. Refers to FCCOB register name, not register address FCCOB Endianness and Multi-Byte Access: The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number.
Page 631 Chapter 29 Flash Memory Module (FTFE) To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field. Then, reprogram the program flash protection byte. Address: 4002_0000h base + 10h offset + (1d × i), where i=0d to 3d Read PROT Write...
Page 632 Memory map and registers Address: 4002_0000h base + 16h offset = 4002_0016h Read EPROT Write Reset * Notes: • x = Undefined at reset. FTFE_FEPROT field descriptions Field Description 7–0 EEPROM Region Protect EPROT For devices with program flash only: Reserved For devices with FlexNVM: Individual EEPROM regions can be protected from alteration by setting the associated EPROT bit.
Page 633 Chapter 29 Flash Memory Module (FTFE) 29.34.8 Data Flash Protection Register (FTFE_FDPROT) The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any FTFE command. Unprotected regions can be changed by both program and erase operations.
Page 634: Functional Description
Functional Description 29.4 Functional Description The following sections describe functional details of the FTFE module. 29.4.1 Program flash memory swap The user can configure the memory map of the program flash space such that either half of the program flash memory can exist at relative address 0x0000. This swap feature enables the lower half of the program flash space to be operational while the upper half is being updated for future use.
Page 635 Chapter 29 Flash Memory Module (FTFE) • FDPROT — • For 2 data flash sizes, protects eight regions of the data flash memory as shown in the following figure FlexNVM 0x0_0000 Data flash size / 8 DPROT0 Data flash size / 8 DPROT1 Data flash size / 8 DPROT2...
Page 636 Functional Description 96KB data flash 0x0_0000 16KB DPROT0 16KB DPROT1 16KB DPROT2 16KB DPROT3 16KB DPROT4 16KB DPROT5 0x1_7FFF 32KB EEPROM backup 0x1_FFFF Figure 29-29. Data flash protection (96KB data flash size) • FEPROT — Protects eight regions of the EEPROM memory as shown in the following figure FlexRAM 0x0_0000...
Page 637: Flexnvm Description
Chapter 29 Flash Memory Module (FTFE) 29.4.3 FlexNVM Description This section describes the FlexNVM memory. This section does not apply for devices that contain only program flash memory. 29.4.3.1 FlexNVM Block Partitioning for FlexRAM The user can configure the FlexNVM block as either: •...
Page 638 Functional Description The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table 29-4).
Page 639 Chapter 29 Flash Memory Module (FTFE) FlexNVM Block 0 FlexNVM Block 1 Data flash 0 Data flash 1 FlexRAM EEPROM partition A EEPROM partition B EEPROM EEPROM backup A backup B Unavailable Subsystem A Subsystem B EEESPLIT = 1/8, 1/4, or 1/2 Size of EEPROM partition A = EEESIZE x EEESPLIT Size of EEPROM partition B = EEESIZE x (1 - EEESPLIT) Data flash 0 and 1 interleaved...
Page 640 Functional Description After a sector in EEPROM backup is full of EEPROM data records, EEPROM data records from the sector holding the oldest data are gradually copied over to a previously- erased EEPROM backup sector. When the sector copy completes, the EEPROM backup sector holding the oldest data is tagged for erase.
Page 641: Interrupts
Chapter 29 Flash Memory Module (FTFE) Figure 29-33. EEPROM backup writes to FlexRAM 29.4.4 Interrupts The FTFE module can generate interrupt requests to the MCU upon the occurrence of various FTFE events. These interrupt events and their associated status and control bits are shown in the following table.
Page 642: Flash Operation In Low-Power Modes
Functional Description 29.4.5 Flash Operation in Low-Power Modes 29.4.5.1 Wait Mode When the MCU enters wait mode, the FTFE module is not affected. The FTFE module can recover the MCU from wait via the command complete interrupt (see Interrupts). 29.4.5.2 Stop Mode When the MCU requests stop mode, if an FTFE command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode.
Page 643: Read While Write (Rww)
Chapter 29 Flash Memory Module (FTFE) 29.4.8 Read while write (RWW) The following simultaneous accesses are allowed for devices with FlexNVM: • The user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and FlexRAM memory space.
Page 644: K22 Sub-Family Reference Manual, Rev. 4, November
Functional Description • The command write sequence used to set FTFE command parameters and launch execution • A description of all FTFE commands available 29.4.10.1 Command Write Sequence FTFE commands are specified using a command write sequence illustrated in Figure 29-34.
Page 645 Chapter 29 Flash Memory Module (FTFE) If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group.
Page 646 Functional Description START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Protection Violation Clear the old errors FPVIOL Check Write 0x30 to FSTAT register Set? Write to the FCCOB registers to load the required command parameter.
Page 647 Chapter 29 Flash Memory Module (FTFE) FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x00 Read 1s Block × × × Verify that a program flash or data flash block is erased.
Page 648 Functional Description FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x0B Program × × × × Program data Section from the Section Program Buffer to a program flash or data flash block.
Page 649 Chapter 29 Flash Memory Module (FTFE) FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x44 Erase All Blocks × × × × Erase all program flash blocks, program flash swap IFR, data flash...
Page 650 Functional Description FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x81 Set FlexRAM × × Switches Function FlexRAM function between RAM and EEPROM. When switching to EEPROM, FlexNVM is not available while...
Page 651 Chapter 29 Flash Memory Module (FTFE) Table 29-31. Flash commands by mode (continued) NVM Normal NVM Special FCMD Command Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x81 Set FlexRAM Function × × × × — — 29.4.10.4 Allowed simultaneous flash operations Only the operations marked 'OK' in the following table are permitted to run simultaneously on the program flash, data flash, and FlexRAM memories.
Page 652: Margin Read Commands
Functional Description Table 29-33. Allowed Simultaneous Memory Operations Program flash X Read Program Phrase Erase Flash Erase Flash Sector Block Program flash Y Read Program Phrase Erase Flash Sector Erase Flash Block 1. P-Flash X refers to any of the P-Flash blocks (0, 1) and P-Flash Y refers to any of the P-Flash blocks (0, 1), but not the same block.
Page 653: Flash Command Descriptions
Chapter 29 Flash Memory Module (FTFE) The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting.
Page 654 Functional Description 29.4.12.1 Read 1s Block command The Read 1s Block command checks to see if an entire program flash or data flash logical block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified. Table 29-34.
Page 655 Chapter 29 Flash Memory Module (FTFE) 29.4.12.2 Read 1s Section command The Read 1s Section command checks if a section of program flash or data flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of 128 bits to be verified.
Page 656 Functional Description 29.4.12.3 Program Check command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. Table 29-40. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x02 (PGMCHK) Flash address [23:16]...
Page 657 Chapter 29 Flash Memory Module (FTFE) Table 29-41. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 Table 29-42. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security...
Page 658 Functional Description Table 29-44. Read Resource Select Codes Resource Select Code Description Resource Size Local Address Range 0x00 Program Flash 0 IFR 1024 Bytes 0x00_0000 - 0x00_03FF 0x00 Program Flash Swap IFR 1024 Bytes 0x04_0000 - 0x04_03FF 0x00 Data Flash 0 IFR 1024 Bytes 0x80_0000 - 0x80_03FF 0x01...
Page 659 Chapter 29 Flash Memory Module (FTFE) Table 29-46. Program Phrase Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value Byte 4 program value Byte 5 program value Byte 6 program value Byte 7 program value 1.
Page 660 Functional Description 29.4.12.6 Erase Flash Block Command The Erase Flash Block operation erases all addresses in a single program flash or data flash block. Table 29-48. Erase Flash Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x08 (ERSBLK) Flash address [23:16] in the flash block to be erased Flash address [15:8] in the flash block to be erased Flash address [7:0] in the flash block to be erased...
Page 661 Chapter 29 Flash Memory Module (FTFE) Table 29-50. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x09 (ERSSCR) Flash address [23:16] in the flash sector to be erased Flash address [15:8] in the flash sector to be erased Flash address [7:0] in the flash sector to be erased 1.
Page 662 Functional Description CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the FTFE has acknowledged it. 29.4.12.7.2 Resuming a Suspended Erase Flash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes.
Page 663 Chapter 29 Flash Memory Module (FTFE) Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE?
Page 664 Functional Description 29.4.12.8 Program Section command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash sector programming).
Page 665 Chapter 29 Flash Memory Module (FTFE) After the Program Section operation has completed, the CCIF flag will set and normal access to the FlexRAM is restored. The contents of the Section Program Buffer is not changed by the Program Section operation. Table 29-53.
Page 666 Functional Description 29.4.12.9 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, EEPROM backup records, and data flash IFR have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'.
Page 667 Chapter 29 Flash Memory Module (FTFE) 29.4.12.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program flash 0 IFR map Program Once field). Access to this field is via 8 records, each 8 bytes long.
Page 668 Functional Description be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command). Each Program Once record can be programmed only once since the program flash 0 IFR cannot be erased. Table 29-59.
Page 669 Chapter 29 Flash Memory Module (FTFE) 29.4.12.12 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 29-61. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the FTFE erases all...
Page 670 Functional Description Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command.
Page 671 Chapter 29 Flash Memory Module (FTFE) Configuration Field. If the backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security is released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the FTFE module occurs.
Page 672 Functional Description Table 29-65. Swap Control Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Current Swap Mode: 0x00 - Uninitialized 0x01 - Ready 0x02 - Update 0x03 - Update-Erased 0x04 - Complete Current Swap Block Status: For devices with FlexNVM: 0x00 - Program flash block 0 at 0x0_0000 0x01 - Program flash block 1 at 0x0_0000 For devices with program flash only:...
Page 673 Chapter 29 Flash Memory Module (FTFE) • 0x04 (Progress Swap to COMPLETE State) - After verifying that the current swap state is UPDATE-ERASED and that the aligned flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0x0000.
Page 674 Functional Description swap system is in the UPDATE or UPDATE-ERASED state. Once the swap system has been initialized, the Erase All Blocks command can be used to uninitialize the swap system. Table 29-66. Swap Control Command Error Handling Swap Error Condition Control Error Bit Code...
Page 675 Chapter 29 Flash Memory Module (FTFE) Block0 Active States Block1 Active States Uninitialized0 0xFFFF 0xFFFF Ready0 Complete1 Reset 0xFFFF 0xFFFF 0x0000 0x0000 Update0 UpErs1 0xFF00 0xFFFF 0x0000 0xFF00 Erase Erase UpErs0 Update1 0xFF00 0x0000 0xFFFF 0xFF00 Complete0 Ready1 Reset 0x0000 0x0000 0xFFFF 0xFFFF...
Page 676 Functional Description Table 29-67. Swap State Report Mapping Case Swap Enable Swap Indicator Swap Indicator Swap State State MGST Active Field Code Block 0xFFFF Uninitialized 0x0000 0xFF00 0x0000 Update 0x0000 0xFF00- 0xFFFF Update-Erased 0x0000 0x0000 0xFFFF Complete 0x0000 0x0000 0xFFFF Ready 0x0000 0x0000...
Page 677 Chapter 29 Flash Memory Module (FTFE) 29.4.12.14.1 Swap state determination During the reset sequence, the state of the swap system is determined by evaluating the IFR Swap Field in the program flash swap IFR and both swap indicators located in the program flash blocks at the swap indicator address stored in the IFR Swap Field.
Page 678 Functional Description Table 29-70. Valid EEPROM Data Set Size Codes EEPROM Data Set Size Code (FCCOB4) EEPROM Data Set Size (Bytes) Subsystem A + B EEESPLIT (FCCOB4[5:4)] EEESIZE (FCCOB4[3:0]) 8 + 24 16 + 16 16 + 16 8 + 56 16 + 48 32 + 32 32 + 32...
Page 679 Chapter 29 Flash Memory Module (FTFE) Table 29-71. Valid FlexNVM Partition Codes FlexNVM Partition Code DEPART Data flash Size (Kbytes) EEPROM-backup Size (Kbytes) (FCCOB5[3:0) 0000 0011 0100 0101 1000 1011 1100 1101 1. FCCOB5[7:4] = 0000 After clearing CCIF to launch the Program Partition command, the FTFE first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data flash IFR are erased.
Page 680 Functional Description 29.4.12.16 Set FlexRAM Function command The Set FlexRAM Function command changes the function of the FlexRAM: • When not partitioned for EEPROM, the FlexRAM is typically used as traditional RAM. • When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM data.
Page 681: Security
Chapter 29 Flash Memory Module (FTFE) When making the FlexRAM available for EEPROM, the FTFE clears the FCNFG[RAMRDY] and FCNFG[EEERDY] flags, overwrites the contents of the FlexRAM allocated for EEPROM with a background pattern of all ones, and copies the existing EEPROM data from the EEPROM backup record space to the FlexRAM.
Page 682 Functional Description Table 29-77. FTFE Access Summary MCU Security State Operating Mode Unsecure Secure NVM Normal Full command set Only the Erase All Blocks and Read 1s All NVM Special Full command set Blocks commands. 29.4.13.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field.
Page 683: Reset Sequence
Chapter 29 Flash Memory Module (FTFE) 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits future use of the Verify Backdoor Access Key command.
Page 684 Functional Description K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 685: Overview
Chapter 30 EzPort 30.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The EzPort module is a serial flash programming interface that enables In-System Programming (ISP) of flash memory contents in a 32-bit general-purpose microcontroller.
Page 686: Block Diagram
Overview 30.1.1 Block diagram EzPort Enabled EZP_CS EZP_CK Flash EzPort Controller EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 30-1. EzPort block diagram 30.1.2 Features EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. •...
Page 687: External Signal Descriptions
Chapter 30 EzPort • Enabled — When enabled, the EzPort steals access to the flash memory, preventing access from other cores or peripherals. The rest of the microcontroller is disabled to avoid conflicts. The flash is configured for NVM Special mode. •...
Page 688: Ezport Chip Select (Ezp_Cs)
Command definition The maximum frequency of the EzPort clock is half the system clock frequency for all commands, except when executing the Read Data or Read FlexRAM commands. When executing the Read Data or Read FlexRAM commands, the EzPort clock has a maximum frequency of 1/8 the system clock frequency.
Page 689: Command Descriptions
Chapter 30 EzPort Table 30-2. EzPort commands (continued) Address Accepted when Command Description Code Data Bytes Bytes secure? READ Flash Read Data 0x03 FAST_READ Flash Read Data at High Speed 0x0B Flash Section Program 0x02 416 - SECTION Flash Sector Erase 0xD8 Flash Bulk Erase 0xC7...
Page 690 Command definition 30.3.1.3 Read Status Register The Read Status Register (RDSR) command returns the contents of the EzPort status register. Table 30-3. EzPort status register FLEXRAM BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 2.
Page 691 Chapter 30 EzPort Table 30-4. EzPort status register field description (continued) Field Description Write error flag Indicates whether there has been an error while executing a write command (SP, SE, BE, WRFCCOB, or WRFLEXRAM). The WEF flag will set if Flash Access Error Flag (ACCERR), Flash Protection Violation (FPVIOL), or Memory Controller Command Completion Status (MGSTAT0) inside the flash memory is set at the completion of the write command.
Page 692 Command definition 30.3.1.6 Section Program The Section Program (SP) command programs up to one section of flash memory that has previously been erased. Please see the Flash Memory chapter for a definition of section size. The starting address of the memory to program is sent after the command word and must be a 32-bit aligned address with the two LSBs being zero.128-bit aligned address with the four LSBs being zero.
Page 693 Chapter 30 EzPort 30.3.1.8 Bulk Erase The Bulk Erase (BE) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. Flash security is disabled upon successful completion of the BE command. Attempts to issue a BE command while the BEDIS and FS fields are set results in the WEF flag being set in the EzPort status register.
Page 694 Command definition 30.3.1.11 Read FCCOB Registers at High Speed The Read FCCOB Registers at High Speed (FAST_RDFCCOB) command allows the user to read the contents of the flash common command object registers. After receiving the command, EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B.
Page 695: Flash Memory Map For Ezport Access
Chapter 30 EzPort The Read FlexRAM (RDFLEXRAM) command returns data from the FlexRAM. If the FlexRAM is configured for EEPROM operation, the RDFLEXRAM command can effectively be used to read data from EEPROM flash memory. Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing.
Page 696 Flash memory map for EzPort access K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 697: External Bus Interface (Flexbus)
Chapter 31 External Bus Interface (FlexBus) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations.
Page 698: Features
Signal descriptions 31.1.2 Features FlexBus offers the following features: • Six independent, user-programmable chip-select signals (FB_CS5 –FB_CS0) • 8-bit, 16-bit, and 32-bit port sizes with configuration for multiplexed or nonmultiplexed address and data buses • 8-bit, 16-bit, 32-bit, and 16-byte transfers •...
Page 699 Chapter 31 External Bus Interface (FlexBus) Table 31-1. FlexBus signal descriptions (continued) Signal Function FB_CS5–FB_CS0 General Purpose Chip-Selects—Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM].
Page 700 Signal descriptions Table 31-1. FlexBus signal descriptions (continued) Signal Function FB_TSIZ1–FB_TSIZ0 Transfer Size—Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. •...
Page 701: Memory Map/Register Definition
Chapter 31 External Bus Interface (FlexBus) Table 31-1. FlexBus signal descriptions (continued) Signal Function FB_TA Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral drives FB_TA to terminate the transfer.
Page 702: Chip Select Address Register (Fb_Csarn)
Memory Map/Register Definition FB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_C000 Chip Select Address Register (FB_CSAR0) 0000_0000h 31.3.1/702 4000_C004 Chip Select Mask Register (FB_CSMR0) 0000_0000h 31.3.2/703 4000_C008 Chip Select Control Register (FB_CSCR0) 0000_0000h 31.3.3/704 4000_C00C Chip Select Address Register (FB_CSAR1)
Page 703: Chip Select Mask Register (Fb_Csmrn)
Chapter 31 External Bus Interface (FlexBus) FB_CSARn field descriptions (continued) Field Description NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. See the chip memory map for the applicable FlexBus "expansion"...
Page 704: K22 Sub-Family Reference Manual, Rev. 4, November
Memory Map/Register Definition FB_CSMRn field descriptions (continued) Field Description NOTE: At reset, FB_CS0 will fire for any access to the FlexBus memory region. CSMR0[V] must be set as part of the chip select initialization sequence to allow other chip selects to function as programmed.
Page 705 Chapter 31 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description Used only when the SWSEN bit is 1b. Specifies the number of wait states inserted before an internal transfer acknowledge is generated for a burst transfer (except for the first termination, which is controlled by WS).
Page 706 Memory Map/Register Definition FB_CSCRn field descriptions (continued) Field Description 15–10 Wait States Specifies the number of wait states inserted after FlexBus asserts the associated chip-select and before an internal transfer acknowledge is generated (WS = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
Page 707: Chip Select Port Multiplexing Control Register (Fb_Cspmcr)
Chapter 31 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
Page 708: Functional Description
Functional description FB_CSPMCR field descriptions (continued) Field Description 0000 FB_CS5 0001 FB_TSIZ1 0010 FB_BE_23_16 Any other value Reserved 19–16 FlexBus Signal Group 4 Multiplex control GROUP4 Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals. 0000 FB_TBST 0001 FB_CS2 0010...
Page 709: Address Comparison
Chapter 31 External Bus Interface (FlexBus) 31.4.2 Address comparison When a bus cycle is routed to FlexBus, FlexBus compares the transfer address to the base address (see CSAR[BA]) and base address mask (see CSMR[BAM]). This table describes how FlexBus decides to assert a chip-select and complete the bus cycle based on the address comparison.
Page 710: Data Transfer Signals
Functional description 31.4.6 Data transfer signals Data transfers between FlexBus and the external memory or peripheral involve these signals: • Address/data bus (FB_AD31–FB_AD0 ) • Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_R/W, FB_BEn) • Attribute signals (FB_TBST, FB_TSIZ1–FB_TSIZ0) 31.4.7 Signal transitions These signals change on the rising edge of the FlexBus clock (FB_CLK): •...
Page 711 Chapter 31 External Bus Interface (FlexBus) In BLS = 0 mode, the byte enables always correspond to the same byte lanes, regardless of which port size that you are using. Byte Select FB_BE_7_0 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 External FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0] Data Bus 32-Bit Port...
Page 712: Address/Data Bus Multiplexing
Functional description 31.4.9 Address/data bus multiplexing FlexBus supports a single 32-bit wide multiplexed address and data bus (FB_AD31– FB_AD0). FlexBus always drives the full 32-bit address on the first clock of a bus cycle. During the data phase, the FB_AD31– FB_AD0 lines used for data are determined by the programmed port size and BLS setting for the corresponding chip-select.
Page 713: Data Transfer States
Chapter 31 External Bus Interface (FlexBus) 31.4.10 Data transfer states Basic data transfers occur in four clocks or states. (See Figure 31-26 Figure 31-28 examples of basic data transfers.) The FlexBus state machine controls the data-transfer operation. This figure shows the state-transition diagram for basic read and write cycles. Next Cycle Wait States The states are described in this table.
Page 714: Flexbus Timing Examples
Functional description 31.4.11 FlexBus Timing Examples Note The timing diagrams throughout this section use signal names that may not be included on your particular device. Ignore these extraneous signals. Note Throughout this section: • FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus •...
Page 715 Chapter 31 External Bus Interface (FlexBus) Note The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial.
Page 716 Functional description FlexBus External Memory/Peripheral 1. Set FB_R/W to write. 2. Place address on the external address signals. 3. Assert transfer start. 1. Decode address. 1. Negate transfer start. 2. Assert FB_CSn. 3. Drive data. 1. Select the appropriate slave device. 1.
Page 717 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-28. Basic Write-Bus Cycle 31.4.11.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. 31.4.11.3.1 Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait States The following figure illustrates the basic byte read transfer to an 8-bit device with no wait states:...
Page 718 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 01 Figure 31-29. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24].
Page 719 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=01 Figure 31-30. Single Byte-Write Transfer 31.4.11.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States The following figure illustrates the basic word read transfer to a 16-bit device with no wait states.
Page 720 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 10 Figure 31-31. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16].
Page 721 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 31-32. Single Word-Write Transfer 31.4.11.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device.
Page 722 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 31-33. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 723 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=00 Figure 31-34. Longword-Write Transfer 31.4.11.4 Timing Variations The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data.
Page 724 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-35. Basic Read-Bus Cycle (No Wait States) K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 725 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-36. Basic Write-Bus Cycle (No Wait States) If wait states are used, the S1 state repeats continuously until the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.
Page 726 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-37. Read-Bus Cycle (One Wait State) K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 727 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-38. Write-Bus Cycle (One Wait State) 31.4.11.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis.
Page 728 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-39. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 729 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-40. Write-Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, a programmable address hold option for each chip select exists.
Page 730 Functional description FB_CLK Address FB_A[Y] FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-41. Read Cycle with Two-Clock Address Hold (No Wait States) K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 731 Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-42. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. K22 Sub-Family Reference Manual, Rev.
Page 732: Burst Cycles
Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-43. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 31.4.12 Burst cycles The chip can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination.
Page 733 Chapter 31 External Bus Interface (FlexBus) 31.4.12.2 Transfer size and port size translation With bursting disabled, any transfer larger than the port size breaks into multiple individual transfers (e.g. <Addr><Data><Addr+1><Data><Addr+2><Data>). With bursting enabled, any transfer larger than the port size results in a burst cycle of multiple beats (e.g.
Page 734 Functional description 32-bit Read Burst from 8-bit port 2-1-1-1, with no wait states FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_TBST FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 11 31.4.12.4 32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states) The following figure shows a 32-bit write to an 8-bit external chip with burst enabled.
Page 735 Chapter 31 External Bus Interface (FlexBus) 32-bit Write Burst to 8-bit port 3-1-1-1, with no wait states FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data AA=1 FB_TBST AA=0 FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ...
Page 736 Functional description FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Data Add+2 Add+3 Add+1 Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 01 TSIZ = 00 31.4.12.6 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) The following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats.
Page 737 Chapter 31 External Bus Interface (FlexBus) 32-bit Read Burst from 8-bit port 3-2-2-2, with 1 wait state FB_CLK FB_A[Y] Address Add+3 Add+1 Add+2 FB_D[X] Address Data Data Data Data FB_TBST FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00...
Page 738 Functional description 32-bit Write Burst to 8-bit port 3-2-2-2, with 1 wait state FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_TBST FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 31.4.12.8 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold) If address setup and hold are used, only the first and last beat of the burst cycle are...
Page 739 Chapter 31 External Bus Interface (FlexBus) 32-bit Read Burst from 8-bit port 3-1-1-1, with address setup and hold FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_TBST FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0]...
Page 740: Extended Transfer Start/Address Latch Enable
Functional description 32-bit Write Burst to 8-bit port 3-1-1-1, with address setup and hold FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_TBST FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=11 31.4.13 Extended Transfer Start/Address Latch Enable The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address and attributes are valid.
Page 741: Bus Errors
Chapter 31 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 31-44. Read-Bus Cycle with CSCRn[EXTS] = 1 (One Wait State) 31.4.14 Bus errors These types of accesses cause a transfer to terminate with a bus error: •...
Page 742: Initialization/Application Information
Initialization/Application Information 31.5 Initialization/Application Information 31.5.1 Initializing a chip-select To initialize a chip-select: 1. Write to the associated CSAR. 2. Write to the associated CSCR. 3. Write to the associated CSMR, including writing 1b to the Valid field (CSMRn[V]). 31.5.2 Reconfiguring a chip-select To reconfigure a previously-used chip-select: 1.
Page 743: Introduction
Chapter 32 Cyclic Redundancy Check (CRC) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard.
Page 744: Block Diagram
Memory map and register descriptions 32.1.2 Block diagram The following is a block diagram of the CRC. FXOR TOTR CRC Data Register [31:24] CRC Data Register Seed Reverse [23:16] [31:24] Logic [15:8] Reverse [23:16] CRC Data [7:0] Logic Logic [15:8] [7:0] Checksum CRC Polynomial...
Page 745: Crc Data Register (Crc_Data)
Chapter 32 Cyclic Redundancy Check (CRC) 32.2.1 CRC Data register (CRC_DATA) The CRC Data register contains the value of the seed, data, and checksum. When CTRL[WAS] is set, any write to the data register is regarded as the seed value. When CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC computation.
Page 746: Crc Polynomial Register (Crc_Gpoly)
Memory map and register descriptions 32.2.2 CRC Polynomial register (CRC_GPOLY) This register contains the value of the polynomial for the CRC calculation. The HIGH field contains the upper 16 bits of the CRC polynomial, which are used only in 32-bit CRC mode.
Page 747: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 32 Cyclic Redundancy Check (CRC) CRC_CTRL field descriptions Field Description 31–30 Type Of Transpose For Writes Define the transpose configuration of the data written to the CRC data register. See the description of the transpose feature for the available transpose options. No transposition.
Page 748: Crc Initialization/Reinitialization
Functional description 32.3.1 CRC initialization/reinitialization To enable the CRC calculation, the user must program the WAS, POLYNOMIAL, and necessary parameters for transpose and CRC result inversion in the applicable registers. Asserting CTRL[WAS] enables the programming of the seed value into the CRC data register.
Page 749: Transpose Feature
Chapter 32 Cyclic Redundancy Check (CRC) 32.3.2.2 32-bit CRC To compute a 32-bit CRC: 1. Set CRC_CTRL[TCRC] to enable 32-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature CRC result complement for details.
Page 750 Functional description No transposition occurs. 2. CTRL[TOT] or CTRL[TOTR] is 01 Bits in a byte are transposed, while bytes are not transposed. reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]} Figure 32-5. Transpose type 01 3. CTRL[TOT] or CTRL[TOTR] is 10 Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 32-6.
Page 751: Crc Result Complement
Chapter 32 Cyclic Redundancy Check (CRC) Figure 32-7. Transpose type 11 NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only.
Page 752 Functional description K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 753: Introduction
Chapter 33 Analog-to-Digital Converter (ADC) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device.
Page 754: Block Diagram
Introduction • Configurable sample time and conversion speed/power • Conversion complete/hardware average complete flag and interrupt • Input clock selectable from up to four sources • Operation in Low-Power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock •...
Page 755: Adc Signal Descriptions
Chapter 33 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion trigger SC1n ADHWTSn control A D T R G ADHWT (SC2, CFG1, CFG2) C o m p a re tru e Control Registers A D A C K E N Async Clock Gen Interrupt ADACK A D C K...
Page 756: Voltage Reference Select
ADC Signal Descriptions Table 33-1. ADC Signal Descriptions Signal Description DADP3–DADP0 Differential Analog Channel Inputs DADM3–DADM0 Differential Analog Channel Inputs Single-Ended Analog Channel Inputs Voltage Reference Select High REFSH Voltage Reference Select Low REFSL Analog Power Supply Analog Ground 33.2.1 Analog Power (V The ADC analog portion uses V as its power connection.
Page 757: Analog Channel Inputs (Adx)
Chapter 33 Analog-to-Digital Converter (ADC) In some packages, V is connected in the package to V and V to V . If REFH REFL externally available, the positive reference(s) may be connected to the same potential as or may be driven by an external source to a level between the minimum Ref Voltage High and the V potential.
Page 758 Register definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_B020 Status and Control Register 2 (ADC0_SC2) 0000_0000h 33.3.6/767 4003_B024 Status and Control Register 3 (ADC0_SC3) 0000_0000h 33.3.7/769 4003_B028 ADC Offset Correction Register (ADC0_OFS) 0000_0004h 33.3.8/771 4003_B02C ADC Plus-Side Gain Register (ADC0_PG)
Page 759: Adc Status And Control Registers 1 (Adcx_Sc1N)
Chapter 33 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400B_B020 Status and Control Register 2 (ADC1_SC2) 0000_0000h 33.3.6/767 400B_B024 Status and Control Register 3 (ADC1_SC3) 0000_0000h 33.3.7/769 400B_B028 ADC Offset Correction Register (ADC1_OFS) 0000_0004h 33.3.8/771...
Page 760 Register definition trigger mode. See the chip configuration information about the number of SC1n registers specific to this device. The SC1n registers have identical fields, and are used in a "ping- pong" approach to control ADC operation. At any one point in time, only one of the SC1n registers is actively controlling ADC conversions.
Page 761 Chapter 33 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare result is true.
Page 762: Adc Configuration Register 1 (Adcx_Cfg1)
Register definition ADCx_SC1n field descriptions (continued) Field Description 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 01111 When DIFF=0, AD15 is selected as input;...
Page 763 Chapter 33 Analog-to-Digital Converter (ADC) ADCx_CFG1 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Low-Power Configuration ADLPC Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required.
Page 764: Adc Configuration Register 2 (Adcx_Cfg2)
Register definition 33.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: Base address + Ch offset Reset ADLSTS Reset ADCx_CFG2 field descriptions...
Page 765: Adc Data Result Register (Adcx_Rn)
Chapter 33 Analog-to-Digital Converter (ADC) ADCx_CFG2 field descriptions (continued) Field Description Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 1–0 Long Sample Time Select ADLSTS Selects between the extended sample times when long sample time is selected, that is, when CFG1[ADLSMP]=1.
Page 766: Compare Value Registers (Adcx_Cvn)
Register definition Table 33-43. Data result register description (continued) Conversion D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format mode 9-bit differential Sign-extended 2's complement 8-bit single- Unsigned right- ended justified NOTE S: Sign bit or sign bit extension;...
Page 767: Status And Control Register 2 (Adcx_Sc2)
Chapter 33 Analog-to-Digital Converter (ADC) ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Compare Value. 33.3.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module.
Page 768 Register definition ADCx_SC2 field descriptions (continued) Field Description Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. Conversion not in progress. Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion.
Page 769: Status And Control Register 3 (Adcx_Sc3)
Chapter 33 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description Reserved Reserved 33.3.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module. Address: Base address + 24h offset Reset AVGS...
Page 770 Register definition ADCx_SC3 field descriptions (continued) Field Description calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC registers or the results will be invalid and CALF will set. Setting CAL will abort any current conversion. Calibration Failed Flag CALF Displays the result of the calibration sequence.
Page 771: Adc Offset Correction Register (Adcx_Ofs)
Chapter 33 Analog-to-Digital Converter (ADC) 33.3.8 ADC Offset Correction Register (ADCx_OFS) The ADC Offset Correction Register (OFS) contains the user-selected or calibration- generated offset error correction value. This register is a 2’s complement, left-justified, 16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn.
Page 772: Adc Minus-Side Gain Register (Adcx_Mg)
Register definition ADCx_PG field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Plus-Side Gain 33.3.10 ADC Minus-Side Gain Register (ADCx_MG) The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side input in differential mode.
Page 773: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 33 Analog-to-Digital Converter (ADC) Address: Base address + 34h offset CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLPD 33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description.
Page 774: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Register definition ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLP4 33.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: Base address + 40h offset CLP3 Reset...
Page 775: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Chapter 33 Analog-to-Digital Converter (ADC) 33.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: Base address + 48h offset CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLP1...
Page 776: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Register definition 33.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD) The Minus-Side General Calibration Value (CLMx) registers contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0].
Page 777: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Chapter 33 Analog-to-Digital Converter (ADC) 33.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4) For more information, see CLMD register description. Address: Base address + 5Ch offset CLM4 Reset ADCx_CLM4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLM4...
Page 778: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Register definition 33.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2) For more information, see CLMD register description. Address: Base address + 64h offset CLM2 Reset ADCx_CLM2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–0 Calibration Value CLM2...
Page 779: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
Chapter 33 Analog-to-Digital Converter (ADC) 33.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0) For more information, see CLMD register description. Address: Base address + 6Ch offset CLM0 Reset ADCx_CLM0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLM0...
Page 780: Clock Select And Divide Control
Functional description The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations. NOTE For the chip specific modes of operation, see the power management information of this MCU.
Page 781: Voltage Reference Selection
Chapter 33 Analog-to-Digital Converter (ADC) 33.4.2 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (V and V ) used for conversions. Each pair contains a REFSH REFSL positive reference that must be between the minimum Ref Voltage High and V , and a ground reference that must be at the same potential as V...
Page 782: Conversion Control
Functional description When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received. For example: • ADHWTSA active selects RA register • ADHWTSn active selects Rn register The conversion complete flag associated with the ADHWTSn received, that is, SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1.
Page 783 Chapter 33 Analog-to-Digital Converter (ADC) Note Selecting more than one ADHWTSn prior to a conversion completion will result in unknown results. To avoid this, select only one ADHWTSn prior to a conversion completion. • Following the transfer of the result to the data registers when continuous conversion is enabled, that is, when ADCO=1.
Page 784 Functional description • Writing to SC1A while it is actively controlling a conversion, aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s. Writing to any of the SC1B–SC1n registers while that specific SC1B–SC1n register is actively controlling a conversion aborts the current conversion.
Page 785 Chapter 33 Analog-to-Digital Converter (ADC) ADC configuration Sample time (ADCK cycles) CFG1[ADLSMP] CFG2[ADLSTS] CFG2[ADHSC] First or Single Subsequent The total conversion time depends upon: • The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS] • The MCU bus frequency • The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF] •...
Page 786 Functional description The maximum total conversion time for all configurations is summarized in the equation below. See the following tables for the variables referenced in the equation. Figure 33-92. Conversion time equation Table 33-104. Single or first continuous time adder (SFCAdder) CFG1[AD CFG2[AD CFG1[ADICLK]...
Page 787 Chapter 33 Analog-to-Digital Converter (ADC) Table 33-107. Long sample time adder (LSTAdder) Long sample time adder CFG1[ADLSMP] CFG2[ADLSTS] (LSTAdder) 0 ADCK cycles 20 ADCK cycles 12 ADCK cycles 6 ADCK cycles 2 ADCK cycles Table 33-108. High-speed conversion time adder (HSCAdder) CFG2[ADHSC] High-speed conversion time adder (HSCAdder) 0 ADCK cycles...
Page 788 Functional description Table 33-109. Typical conversion time (continued) Variable Time AverageNum 20 ADCK cycles LSTAdder HSCAdder The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting conversion time is 3.75 µs.
Page 789 Chapter 33 Analog-to-Digital Converter (ADC) • 8-bit Single-Ended mode with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 20 MHz • Long sample time disabled • High-speed conversion enabled The conversion time for this conversion is calculated by using the Figure 33-92, and the...
Page 790: Automatic Compare Function
Functional description Note The hardware average function can perform conversions on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the hardware average is completed if SC1n[AIEN] was set. 33.4.5 Automatic compare function The compare function can be configured to check whether the result is less than or greater-than-or-equal-to a single compare value, or, if the result falls within or outside a range determined by two compare values.
Page 791: Calibration Function
Chapter 33 Analog-to-Digital Converter (ADC) If the condition selected evaluates true, SC1n[COCO] is set. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, SC1n[COCO] is not set and the conversion result data will not be transferred to the result register, Rn.
Page 792 Functional description To initiate calibration, the user sets SC3[CAL] and the calibration will automatically begin if the SC2[ADTRG] is 0. If SC2[ADTRG] is 1, SC3[CAL] will not get set and SC3[CALF] will be set. While calibration is active, no ADC register can be written and no stop mode may be entered, or the calibration routine will be aborted causing SC3[CAL] to clear and SC3[CALF] to set.
Page 793: User-Defined Offset Function
Chapter 33 Analog-to-Digital Converter (ADC) 33.4.7 User-defined offset function OFS contains the user-selected or calibration-generated offset error correction value. This register is a 2’s complement, left-justified. The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation.
Page 794: Temperature Sensor
Functional description 33.4.8 Temperature sensor The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs. The following equation provides an approximate transfer function of the temperature sensor. Figure 33-93. Approximate transfer function of the temperature sensor where: •...
Page 795: Mcu Normal Stop Mode Operation
Chapter 33 Analog-to-Digital Converter (ADC) The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in Wait mode. The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU. See the Chip Configuration information on ALTCLK specific to this MCU.
Page 796: Mcu Low-Power Stop Mode Operation
Initialization information If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Normal Stop mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. The result register, Rn, will contain the data from the first completed conversion that occurred during Normal Stop mode.
Page 797: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 33 Analog-to-Digital Converter (ADC) 33.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is: 1. Calibrate the ADC by following the calibration instructions in Calibration function. 2.
Page 798: Application Information
Application information Bit 7 COCO Read-only flag which is set when a conversion completes. Bit 6 AIEN Conversion complete interrupt enabled. Bit 5 DIFF 0 Single-ended conversion selected. Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion.
Page 799 Chapter 33 Analog-to-Digital Converter (ADC) 33.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: • V and V available as separate pins—When available on a separate pin, both and V must be connected to the same voltage potential as their corresponding MCU digital supply, V...
Page 800: Sources Of Error
Application information AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good high-frequency characteristics.
Page 801 Chapter 33 Analog-to-Digital Converter (ADC) RAS = External analog source resistance SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2 LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or...
Page 802 Application information • For software triggered conversions, immediately follow the write to SC1 with a Wait instruction or Stop instruction. • For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces V noise but increases effective conversion time due to stop recovery.
Page 803 Chapter 33 Analog-to-Digital Converter (ADC) For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB. 33.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms.
Page 804 Application information This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. • Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. •...
Page 805: Introduction
Chapter 34 Comparator (CMP) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation.
Page 806: Bit Dac Key Features
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications •...
Page 807: Anmux Key Features
Chapter 34 Comparator (CMP) 34.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 34.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K22 Sub-Family Reference Manual, Rev.
Page 808: Cmp Block Diagram
CMP block diagram VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 34-1. CMP, DAC and ANMUX block diagram 34.6 CMP block diagram The following figure shows the block diagram for the CMP module.
Page 809 Chapter 34 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSCTRL[1:0] Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided prescaler FILT_PER CGMUX clock Figure 34-2. Comparator module block diagram In the CMP block diagram: •...
Page 810: Memory Map/Register Definitions
Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. •...
Page 811: Cmp Control Register 1 (Cmpx_Cr1)
Chapter 34 Comparator (CMP) CMPx_CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Represents the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state.
Page 812 Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description Sampling mode is not selected. Sampling mode is selected. Windowing Enable At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set and WE is cleared.
Page 813: Cmp Filter Period Register (Cmpx_Fpr)
Chapter 34 Comparator (CMP) 34.7.3 CMP Filter Period Register (CMPx_FPR) Address: Base address + 2h offset Read FILT_PER Write Reset CMPx_FPR field descriptions Field Description 7–0 Filter Sample Period FILT_PER Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter.
Page 814: Dac Control Register (Cmpx_Daccr)
Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. Interrupt is disabled.
Page 815: Mux Control Register (Cmpx_Muxcr)
Chapter 34 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in 5–0 DAC Output Voltage Select VOSEL Selects an output voltage from one of 64 distinct levels. /64) * (VOSEL[5:0] + 1) , so the DACO range is from V /64 to V DACO = (V...
Page 816: Functional Description
Functional description CMPx_MUXCR field descriptions (continued) Field Description NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 34.8 Functional description The CMP module can be used to compare two analog input voltages applied to INP and INM.
Page 817 Chapter 34 Comparator (CMP) The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications.
Page 818 Functional description For cases where a comparator is used to drive a fault input, for example, for a motor- control module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry.
Page 819 Chapter 34 Comparator (CMP) NOTE See the chip configuration section for the source of sample/ window input. The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed.
Page 820 Functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived.
Page 821 Chapter 34 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0] > 0x01 Polarity Interrupt Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1...
Page 822 Functional description Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0 > 0x01 Polarity Filter Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=0 Figure 34-31.
Page 823 Chapter 34 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 34-32. Windowed mode operation Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSCTR[1:0] 0x01 Interrupt Polarity Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock...
Page 824 Functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 34.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 34-32, and adds resampling of COUTA to generate COUT.
Page 825: Power Modes
Chapter 34 Comparator (CMP) 34.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function.
Page 826: Startup And Operation
Functional description 34.8.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 827: Low-Pass Filter
Chapter 34 Comparator (CMP) During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path.
Page 828 Functional description Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior.
Page 829: Cmp Interrupts
Chapter 34 Comparator (CMP) Table 34-30. Comparator sample/filter maximum latencies (continued) CR1[ CR1[ CR1[ CR0[FILTER FPR[FILT_P Mode # Operation Maximum latency _CNT] > 0x01 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T 0x00...
Page 830: Cmp Asyncrhonous Dma Support
CMP Asyncrhonous DMA support The comparator can remain functional in STOP modes. When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes.
Page 831: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 34 Comparator (CMP) DACEN VOSEL[5:0] VRSEL DACO Figure 34-36. 6-bit DAC block diagram 34.13 DAC functional description This section provides DAC functional description. 34.13.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder •...
Page 832: Dac Interrupts
DAC interrupts 34.16 DAC interrupts This module has no interrupts. K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 833: Introduction
Chapter 35 12-bit Digital-to-Analog Converter (DAC) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC.
Page 834: Memory Map/Register Definition
Memory map/register definition DACREF_2 DACREF_1 DACRFS DACRFS AMP buffer DACEN LPEN DACDAT[11:0] Hardware trigger DACBFWMF & DACBWIEN DACSWTRG Data Buffer DACBFWM DACBFRPTF dac_interrupt & DACBFEN DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 35-1. DAC block diagram 35.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions.
Page 835 Chapter 35 12-bit Digital-to-Analog Converter (DAC) DAC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400C_C000 DAC Data Low Register (DAC0_DAT0L) 35.4.1/836 400C_C001 DAC Data High Register (DAC0_DAT0H) 35.4.2/836 400C_C002 DAC Data Low Register (DAC0_DAT1L) 35.4.1/836 400C_C003 DAC Data High Register (DAC0_DAT1H) 35.4.2/836...
Page 836: Dac Data Low Register (Dacx_Datnl)
Memory map/register definition 35.4.1 DAC Data Low Register (DACx_DATnL) Address: 400C_C000h base + 0h offset + (2d × i), where i=0d to 15d Read DATA0 Write Reset DACx_DATnL field descriptions Field Description 7–0 When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following DATA0 formula: V * (1 + DACDAT0[11:0])/4096...
Page 837: Dac Control Register (Dacx_C0)
Chapter 35 12-bit Digital-to-Analog Converter (DAC) Address: 400C_C000h base + 20h offset = 400C_C020h Read DACBFWM DACBFRPT DACBFRPB Write Reset DACx_SR field descriptions Field Description 7–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC Buffer Watermark Flag DACBFWMF The DAC buffer read pointer has not reached the watermark level.
Page 838: Dac Control Register 1 (Dacx_C1)
Memory map/register definition DACx_C0 field descriptions (continued) Field Description The DAC selects DACREF_1 as the reference voltage. The DAC selects DACREF_2 as the reference voltage. DAC Trigger Select DACTRGSEL The DAC hardware trigger is selected. The DAC software trigger is selected. DAC Software Trigger DACSWTRG Active high.
Page 839: Dac Control Register 2 (Dacx_C2)
Chapter 35 12-bit Digital-to-Analog Converter (DAC) DACx_C1 field descriptions Field Description DMA Enable Select DMAEN DMA is disabled. DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. 6–5 This field is reserved.
Page 840: Functional Description
Functional description DACx_C2 field descriptions (continued) Field Description Keeps the current value of the buffer read pointer. 3–0 DAC Buffer Upper Limit DACBFUP Selects the upper limit of the DAC buffer. The buffer read pointer cannot exceed it. 35.5 Functional description The 12-bit DAC module can select one of the two reference inputs—DACREF_1 and DACREF_2 as the DAC reference voltage, V by C0[DACRFS].
Page 841: Dma Operation
Chapter 35 12-bit Digital-to-Analog Converter (DAC) set when the DAC buffer read pointer has reached the position defined by C1[DACBFWM]. C1[DACBFWM] can be used to generate an interrupt when the DAC buffer read pointer is between 1 to 4 words from C2[DACBFUP]. 35.5.1.2 Modes of DAC data buffer operation The following table describes the different modes of data buffer operation for the DAC module.
Page 842 Functional description Table 35-80. Modes of operation Modes of operation Description Wait mode The DAC will operate normally, if enabled. If enabled, the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop. Stop mode In low-power stop modes, the DAC is fully shut down.
Page 843: Introduction
Chapter 36 Voltage Reference (VREFV1) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Voltage Reference(VREF) is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
Page 844: Overview
Introduction 6 BITS 1.75 V Regulator SC[VREFEN] 1.75 V 2 BITS SC[MODE_LV] SC[VREFST] BANDGAP VDDA DEDICATED OUTPUT PIN VREF_OUT 100 nF REGULATION BUFFER Figure 36-1. Voltage reference block diagram 36.1.1 Overview The Voltage Reference provides a buffered reference voltage for use as an external reference.
Page 845: Modes Of Operation
Chapter 36 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Low power buffer mode (output buffer enabled) • High power buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT 36.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes.
Page 846: K22 Sub-Family Reference Manual, Rev. 4, November
Memory Map and Register Definition 36.2 Memory Map and Register Definition VREF memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_4000 VREF Trim Register (VREF_TRM) See section 36.2.1/846 4007_4001 VREF Status and Control Register (VREF_SC) 36.2.2/847 36.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference.
Page 847: Vref Status And Control Register (Vref_Sc)
Chapter 36 Voltage Reference (VREFV1) 36.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the buffer mode to be used. Address: 4007_4000h base + 1h offset = 4007_4001h Read VREFST VREFEN...
Page 848: Functional Description
Functional Description VREF_SC field descriptions (continued) Field Description This bit indicates that the bandgap reference within the Voltage Reference module has completed its startup and stabilization. The module is disabled or not stable. The module is stable. 1–0 Buffer Mode selection MODE_LV These bits select the buffer modes for the Voltage Reference module.
Page 849: Voltage Reference Enabled, Sc[Vrefen] = 1
Chapter 36 Voltage Reference (VREFV1) 36.3.2 Voltage Reference Enabled, SC[VREFEN] = 1 When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should be set by the SC[MODE_LV] bits. 36.3.2.1 SC[MODE_LV]=00 The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield.
Page 850 Initialization/Application Information If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final value. This is the buffer start up delay (Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of Tstup or until SC[VREFST] = 1.
Page 851: Introduction
Chapter 37 Programmable Delay Block (PDB) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved.
Page 852: Implementation
Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support •...
Page 853: Back-To-Back Acknowledgment Connections
Chapter 37 Programmable Delay Block (PDB) • Y—Total number of Pulse-Out's. • y—Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information.
Page 854 Introduction Ack 0 PDBCHnDLY0 Pre-trigger 0 BB[0], TOS[0] EN[0] Ch n pre-trigger 0 Ack m PDBCHnDLYm Pre-trigger m BB[m], TOS[m] EN[m] Ch n pre-trigger m Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD Control DACINTx DAC interval logic trigger x PDBCNT DAC interval...
Page 855: Modes Of Operation
Chapter 37 Programmable Delay Block (PDB) 37.1.6 Modes of operation PDB ADC trigger operates in the following modes: • Disabled—Counter is off, all pre-trigger and trigger outputs are low if PDB is not in back-to-back operation of Bypass mode. • Debug—Counter is paused when processor is in Debug mode, and the counter for the DAC trigger is also paused in Debug mode.
Page 856 Memory map and register definition PDB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_6000 Status and Control register (PDB0_SC) 0000_0000h 37.3.1/857 4003_6004 Modulus register (PDB0_MOD) 0000_FFFFh 37.3.2/859 4003_6008 Counter register (PDB0_CNT) 0000_0000h 37.3.3/860 4003_600C Interrupt Delay register (PDB0_IDLY) 0000_FFFFh...
Page 857: Status And Control Register (Pdbx_Sc)
Chapter 37 Programmable Delay Block (PDB) 37.3.1 Status and Control register (PDBx_SC) Address: 4003_6000h base + 0h offset = 4003_6000h LDMOD Reset PRESCALER TRGSEL MULT Reset PDBx_SC field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–18 Load Mode Select LDMOD...
Page 858 Memory map and register definition PDBx_SC field descriptions (continued) Field Description PDB sequence error interrupt disabled. PDB sequence error interrupt enabled. Software Trigger SWTRIG When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this field resets and restarts the counter.
Page 859: Modulus Register (Pdbx_Mod)
Chapter 37 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description PDB Enable PDBEN PDB disabled. Counter is off. PDB enabled. PDB Interrupt Flag PDBIF This field is set when the counter value is equal to the IDLY register. Writing zero clears this field. PDB Interrupt Enable PDBIE Enables the PDB interrupt.
Page 860: Counter Register (Pdbx_Cnt)
Memory map and register definition PDBx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 PDB Modulus Specifies the period of the counter. When the counter reaches this value, it will be reset back to zero. If the PDB is in Continuous mode, the count begins anew.
Page 861: Channel N Control Register 1 (Pdbx_Chnc1)
Chapter 37 Programmable Delay Block (PDB) PDBx_IDLY field descriptions (continued) Field Description equal to the IDLY. Reading this field returns the value of internal register that is effective for the current cycle of the PDB. 37.3.5 Channel n Control register 1 (PDBx_CHnC1) Each PDB channel has one control register, CHnC1.
Page 862: Channel N Status Register (Pdbx_Chns)
Memory map and register definition 37.3.6 Channel n Status register (PDBx_CHnS) Address: 4003_6000h base + 14h offset + (40d × i), where i=0d to 1d Reset PDBx_CHnS field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–16 PDB Channel Flags The CF[m] bit is set when the PDB counter matches the CHnDLYm.
Page 863: Channel N Delay 1 Register (Pdbx_Chndly1)
Chapter 37 Programmable Delay Block (PDB) 37.3.8 Channel n Delay 1 register (PDBx_CHnDLY1) Address: 4003_6000h base + 1Ch offset + (40d × i), where i=0d to 1d Reset PDBx_CHnDLY1 field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 PDB Channel Delay These bits specify the delay value for the channel's corresponding pre-trigger.
Page 864: Dac Interval N Register (Pdbx_Dacintn)
Memory map and register definition PDBx_DACINTCn field descriptions (continued) Field Description This bit enables the DAC interval trigger. DAC interval trigger disabled. DAC interval trigger enabled. 37.3.10 DAC Interval n register (PDBx_DACINTn) Address: 4003_6000h base + 154h offset + (8d × i), where i=0d to 1d Reset PDBx_DACINTn field descriptions Field...
Page 865: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 37 Programmable Delay Block (PDB) 37.3.12 Pulse-Out n Delay register (PDBx_POnDLY) Address: 4003_6000h base + 194h offset + (4d × i), where i=0d to 2d DLY1 DLY2 Reset PDBx_POnDLY field descriptions Field Description 31–16 PDB Pulse-Out Delay 1 DLY1 These bits specify the delay 1 value for the PDB Pulse-Out.
Page 866 Functional description Each channel is associated with one ADC block. PDB channel n pre-trigger outputs 0 to M and trigger output is connected to ADC hardware trigger select and hardware trigger inputs. The pre-triggers are used to precondition the ADC block prior to the actual trigger.
Page 867: Pdb Trigger Input Source Selection
Chapter 37 Programmable Delay Block (PDB) • the corresponding PDB pre-trigger is disabled, or • the PDB is disabled The channel n trigger output is suppressed when any of the locks of the pre-triggers in channel n is active. If a new pre-trigger m asserts when there is active lock in the PDB channel n, a register flag bit, CHnS[ERR[m]], associated with the pre-trigger m is set.
Page 868: Pulse-Out's
Functional description The DAC interval trigger pulse and the ADC pre-trigger/trigger pulses together allow precise timing of DAC updates and ADC measurements. This is outlined in the typical use case described in the following diagram. MOD, IDLY CHnDLY1 CHnDLY0 DACINTx x3 DACINTx x2 DACINTx counter...
Page 869: Updating The Delay Registers
Chapter 37 Programmable Delay Block (PDB) 37.4.5 Updating the delay registers The following registers control the timing of the PDB operation; and in some of the applications, they may need to become effective at the same time. • PDB Modulus register (MOD) •...
Page 870: Interrupts
Functional description CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 37-58. Registers update with SC[LDMOD] = 00 CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 37-59. Registers update with SC[LDMOD] = x1 37.4.6 Interrupts PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt.
Page 871: Application Information
Chapter 37 Programmable Delay Block (PDB) 37.5 Application information 37.5.1 Impact of using the prescaler and multiplication factor on timing resolution Use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy in terms of peripheral clock cycles (to the modulus of the prescaler X multiplication factor).
Page 872 Application information K22 Sub-Family Reference Manual, Rev. 4, November 2014 Freescale Semiconductor, Inc.
Page 873: Introduction
Chapter 38 FlexTimer Module (FTM) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications.
Page 874: Features
Introduction Motor control and power conversion features have been added through a dedicated set of registers and defaults turn off all new features. The new features, such as hardware deadtime insertion, polarity, fault control, and output forcing and masking, greatly reduce loading on the execution software and are usually each controlled by a group of registers.
Page 875: Modes Of Operation
Chapter 38 FlexTimer Module (FTM) • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels • In Output Compare mode the output signal can be set, cleared, or toggled on match •...
Page 876: Block Diagram
Introduction real time reference or provide the interrupt sources needed to wake the MCU from Wait mode, the power can then be saved by disabling FTM functions before entering Wait mode. 38.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7).
Page 877 Chapter 38 FlexTimer Module (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock prescaler external clock synchronizer (1, 2, 4, 8, 16, 32, 64 or 128) phase A Quadrature decoder phase B QUADEN CPWMS CAPTEST INITTRIGEN initialization...
Page 878: Ftm Signal Descriptions
FTM signal descriptions 38.2 FTM signal descriptions Table 38-1 shows the user-accessible signals for the FTM. Table 38-1. FTM signal descriptions Signal Description Function EXTCLK External clock. FTM external The external clock input signal is used as the FTM counter clock can be selected to drive clock if selected by CLKS[1:0] bits in the SC register.
Page 879: Register Descriptions
Chapter 38 FlexTimer Module (FTM) Note Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0. 38.3.2 Register descriptions Accesses to reserved addresses result in transfer errors. Registers for absent channels are considered reserved.
Page 880 Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 38.3.14/ 4003_8064 Function For Linked Channels (FTM0_COMBINE) 0000_0000h 38.3.15/ 4003_8068 Deadtime Insertion Control (FTM0_DEADTIME) 0000_0000h 38.3.16/ 4003_806C FTM External Trigger (FTM0_EXTTRIG) 0000_0000h 38.3.17/ 4003_8070...
Page 881 Chapter 38 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_9038 Channel (n) Value (FTM1_C5V) 0000_0000h 38.3.7/890 4003_903C Channel (n) Status And Control (FTM1_C6SC) 0000_0000h 38.3.6/888 4003_9040 Channel (n) Value (FTM1_C6V) 0000_0000h 38.3.7/890 4003_9044...
Page 882 Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400B_8000 Status And Control (FTM2_SC) 0000_0000h 38.3.3/885 400B_8004 Counter (FTM2_CNT) 0000_0000h 38.3.4/886 400B_8008 Modulo (FTM2_MOD) 0000_0000h 38.3.5/887 400B_800C Channel (n) Status And Control (FTM2_C0SC) 0000_0000h 38.3.6/888 400B_8010...
Page 883 Chapter 38 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 38.3.20/ 400B_807C Fault Control (FTM2_FLTCTRL) 0000_0000h 38.3.21/ 400B_8080 Quadrature Decoder Control And Status (FTM2_QDCTRL) 0000_0000h 38.3.22/ 400B_8084 Configuration (FTM2_CONF) 0000_0000h 38.3.23/ 400B_8088...
Page 884 Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 38.3.12/ 400B_905C Initial State For Channels Output (FTM3_OUTINIT) 0000_0000h 38.3.13/ 400B_9060 Output Mask (FTM3_OUTMASK) 0000_0000h 38.3.14/ 400B_9064 Function For Linked Channels (FTM3_COMBINE) 0000_0000h 38.3.15/ 400B_9068...
Page 885: Status And Control (Ftmx_Sc)
Chapter 38 FlexTimer Module (FTM) 38.3.3 Status And Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE...
Page 886: Counter (Ftmx_Cnt)
Memory map and register definition FTMx_SC field descriptions (continued) Field Description Timer Overflow Interrupt Enable TOIE Enables FTM overflow interrupts. Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-Aligned PWM Select CPWMS Selects CPWM mode.
Page 887: Modulo (Ftmx_Mod)
Chapter 38 FlexTimer Module (FTM) Address: Base address + 4h offset COUNT Reset FTMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNT 38.3.5 Modulo (FTMx_MOD) The Modulo register contains the modulo value for the FTM counter.
Page 888: Channel (N) Status And Control (Ftmx_Cnsc)
Memory map and register definition 38.3.6 Channel (n) Status And Control (FTMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 38-67. Mode, edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA...
Page 889 Chapter 38 FlexTimer Module (FTM) Table 38-67. Mode, edge, and level selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration See the Dual Edge One-Shot following table Capture Capture mode (Table 38-8). Continuous Capture mode Table 38-68. Dual Edge Capture mode — edge polarity selection ELSnB ELSnA Channel Port Enable...
Page 890: Channel (N) Value (Ftmx_Cnv)
Memory map and register definition FTMx_CnSC field descriptions (continued) Field Description Disable channel interrupts. Use software polling. Enable channel interrupts. Channel Mode Select Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 38-7.
Page 891: Counter Initial Value (Ftmx_Cntin)
Chapter 38 FlexTimer Module (FTM) Address: Base address + 10h offset + (8d × i), where i=0d to 7d Reset FTMx_CnV field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Channel Value Captured FTM counter value of the input modes or the match value for the output modes...
Page 892: K22 Sub-Family Reference Manual, Rev. 4, November
Memory map and register definition Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel.
Page 893: Features Mode Selection (Ftmx_Mode)
Chapter 38 FlexTimer Module (FTM) FTMx_STATUS field descriptions (continued) Field Description No channel event has occurred. A channel event has occurred. Channel 6 Flag CH6F See the register description. No channel event has occurred. A channel event has occurred. Channel 5 Flag CH5F See the register description.
Page 894 Memory map and register definition • Fault control mode and interrupt • Capture Test mode • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT...
Page 895: Synchronization (Ftmx_Sync)
Chapter 38 FlexTimer Module (FTM) FTMx_MODE field descriptions (continued) Field Description Capture test mode is disabled. Capture test mode is enabled. PWM Synchronization Mode PWMSYNC Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. See synchronization.
Page 896 Memory map and register definition NOTE The software trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a potential conflict if used together when SYNCMODE = 0. Use only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen.
Page 897 Chapter 38 FlexTimer Module (FTM) FTMx_SYNC field descriptions (continued) Field Description Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal. Trigger is disabled. Trigger is enabled. PWM Synchronization Hardware Trigger 1 TRIG1 Enables hardware trigger 1 to the PWM synchronization.
Page 898: Initial State For Channels Output (Ftmx_Outinit)
Memory map and register definition 38.3.12 Initial State For Channels Output (FTMx_OUTINIT) Address: Base address + 5Ch offset Reset Reset FTMx_OUTINIT field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Output Initialization Value CH7OI Selects the value that is forced into the channel output when the initialization occurs.
Page 899: Output Mask (Ftmx_Outmask)
Chapter 38 FlexTimer Module (FTM) FTMx_OUTINIT field descriptions (continued) Field Description The initialization value is 0. The initialization value is 1. Channel 2 Output Initialization Value CH2OI Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0.
Page 900 Memory map and register definition FTMx_OUTMASK field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Output Mask CH7OM Defines if the channel output is masked or unmasked. Channel output is not masked.
Page 901: Function For Linked Channels (Ftmx_Combine)
Chapter 38 FlexTimer Module (FTM) 38.3.14 Function For Linked Channels (FTMx_COMBINE) This register contains the control bits used to configure the fault control, synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset...
Page 902 Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description Dual Edge Capture Mode Captures For n = 6 DECAP3 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when FTMEN = 1 and DECAPEN = 1.
Page 903 Chapter 38 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description Deadtime Enable For n = 4 DTEN2 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. The deadtime insertion in this pair of channels is disabled.
Page 904 Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description The fault control in this pair of channels is disabled. The fault control in this pair of channels is enabled. Synchronization Enable For n = 2 SYNCEN1 Enables PWM synchronization of registers C(n)V and C(n+1)V. The PWM synchronization in this pair of channels is disabled.
Page 905 Chapter 38 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Control Enable For n = 0 FAULTEN0 Enables the fault control in channels (n) and (n+1). This field is write protected.
Page 906: Deadtime Insertion Control (Ftmx_Deadtime)
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description Combine Channels For n = 0 COMBINE0 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. Channels (n) and (n+1) are independent.
Page 907: Ftm External Trigger (Ftmx_Exttrig)
Chapter 38 FlexTimer Module (FTM) 38.3.16 FTM External Trigger (FTMx_EXTTRIG) This register: • Indicates when a channel trigger was generated • Enables the generation of a trigger when the FTM counter is equal to its initial value • Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple triggers in one PWM period.
Page 908 Memory map and register definition FTMx_EXTTRIG field descriptions Field Description 31–8 This field is reserved. Reserved Channel Trigger Flag TRIGF Set by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect. If another channel trigger is generated before the clearing sequence is completed, the sequence is reset so TRIGF remains set after the clear sequence is completed for the earlier TRIGF.
Page 909: Channels Polarity (Ftmx_Pol)
Chapter 38 FlexTimer Module (FTM) FTMx_EXTTRIG field descriptions (continued) Field Description The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. 38.3.17 Channels Polarity (FTMx_POL) This register defines the output polarity of the FTM channels. NOTE The safe value that is driven in a channel output when the fault control is enabled and a fault condition is detected is the...
Page 910 Memory map and register definition FTMx_POL field descriptions (continued) Field Description The channel polarity is active high. The channel polarity is active low. Channel 4 Polarity POL4 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high.
Page 911: Fault Mode Status (Ftmx_Fms)
Chapter 38 FlexTimer Module (FTM) 38.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset FTMx_FMS field descriptions Field Description 31–8...
Page 912 Memory map and register definition FTMx_FMS field descriptions (continued) Field Description Write Protection Enable WPEN The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect. Write protection is disabled.
Page 913: Input Capture Filter Control (Ftmx_Filter)
Chapter 38 FlexTimer Module (FTM) FTMx_FMS field descriptions (continued) Field Description If another fault condition is detected at the corresponding fault input before the clearing sequence is completed, the sequence is reset so FAULTF1 remains set after the clearing sequence is completed for the earlier fault condition.
Page 914: Fault Control (Ftmx_Fltctrl)
Memory map and register definition FTMx_FILTER field descriptions (continued) Field Description 11–8 Channel 2 Input Filter CH2FVAL Selects the filter value for the channel input. The filter is disabled when the value is zero. 7–4 Channel 1 Input Filter CH1FVAL Selects the filter value for the channel input.
Page 915 Chapter 38 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field Description NOTE: Writing to this field has immediate effect and must be done only when the fault control or all fault inputs are disabled. Failure to do this could result in a missing fault detection. Fault Input 3 Filter Enable FFLTR3EN Enables the filter for the fault input.
Page 916: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
Memory map and register definition FTMx_FLTCTRL field descriptions (continued) Field Description Fault input is disabled. Fault input is enabled. Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled.
Page 917 Chapter 38 FlexTimer Module (FTM) FTMx_QDCTRL field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Phase A Input Filter Enable PHAFLTREN Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is defined by the CH0FVAL field of FILTER.
Page 918: Configuration (Ftmx_Conf)
Memory map and register definition FTMx_QDCTRL field descriptions (continued) Field Description Quadrature Decoder Mode Enable QUADEN Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 38-7.
Page 919: Ftm Fault Input Polarity (Ftmx_Fltpol)
Chapter 38 FlexTimer Module (FTM) FTMx_CONF field descriptions (continued) Field Description Use of an external global time base is disabled. Use of an external global time base is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–6 BDM Mode BDMMODE...
Page 920 Memory map and register definition FTMx_FLTPOL field descriptions (continued) Field Description Fault Input 3 Polarity FLT3POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. The fault input polarity is active high. A one at the fault input indicates a fault. The fault input polarity is active low.
Page 921: Synchronization Configuration (Ftmx_Synconf)
Chapter 38 FlexTimer Module (FTM) 38.3.24 Synchronization Configuration (FTMx_SYNCONF) This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2, when the hardware trigger j is detected. Address: Base address + 8Ch offset Reset INVC...
Page 922 Memory map and register definition FTMx_SYNCONF field descriptions (continued) Field Description 15–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Software output control synchronization is activated by the software trigger. SWSOC The software trigger does not activate the SWOCTRL register synchronization. The software trigger activates the SWOCTRL register synchronization.
Page 923: Ftm Inverting Control (Ftmx_Invctrl)
Chapter 38 FlexTimer Module (FTM) FTMx_SYNCONF field descriptions (continued) Field Description FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 38.3.25 FTM Inverting Control (FTMx_INVCTRL) This register controls when the channel (n) output becomes the channel (n+1) output, and channel (n+1) output becomes the channel (n) output.
Page 924: Ftm Software Output Control (Ftmx_Swoctrl)
Memory map and register definition FTMx_INVCTRL field descriptions (continued) Field Description Pair Channels 0 Inverting Enable INV0EN Inverting is disabled. Inverting is enabled. 38.3.26 FTM Software Output Control (FTMx_SWOCTRL) This register enables software control of channel (n) output and defines the value forced to the channel (n) output: •...
Page 925 Chapter 38 FlexTimer Module (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 5 Software Output Control Value CH5OCV The software output control forces 0 to the channel output. The software output control forces 1 to the channel output.
Page 926: Ftm Pwm Load (Ftmx_Pwmload)
Memory map and register definition FTMx_SWOCTRL field descriptions (continued) Field Description The channel output is not affected by software output control. The channel output is affected by software output control. Channel 1 Software Output Control Enable CH1OC The channel output is not affected by software output control. The channel output is affected by software output control.
Page 927: Functional Description
Chapter 38 FlexTimer Module (FTM) FTMx_PWMLOAD field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Select CH7SEL Do not include the channel in the matching process. Include the channel in the matching process.
Page 928: Clock Source
Functional description FTM counting is up. Channel (n) is in high-true EPWM mode. PS[2:0] = 001 CNTIN = 0x0000 MOD = 0x0004 CnV = 0x0002 prescaler counter FTM counter channel (n) output counter channel (n) channel (n) counter counter channel (n) overflow match match...
Page 929: Prescaler
Chapter 38 FlexTimer Module (FTM) The external clock passes through a synchronizer clocked by the system clock to assure that counter transitions are properly aligned to system clock transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency.
Page 930 Functional description CNTIN defines the starting value of the count and MOD defines the final value of the count, see the following figure. The value of CNTIN is loaded into the FTM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with the value of CNTIN.
Page 931 Chapter 38 FlexTimer Module (FTM) FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 38-210.
Page 932 Functional description FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN load of CNTIN FTM counter 0x0005 0x0015 0x0016 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 TOF bit set TOF bit set TOF bit Figure 38-211.
Page 933 Chapter 38 FlexTimer Module (FTM) FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 38-212.
Page 934 Functional description • CNTIN = 0x0000, and • MOD = 0xFFFF 38.4.3.4 Counter reset Any one of the following cases resets the FTM counter to the value in the CNTIN register and the channels output to its initial value, except for channels in Output Compare mode. •...
Page 935: Input Capture Mode
Chapter 38 FlexTimer Module (FTM) 38.4.4 Input Capture mode The Input Capture mode is selected when: • DECAPEN = 0 • COMBINE = 0 • CPWMS = 0 • MSnB:MSnA = 0:0, and • ELSnB:ELSnA ≠ 0:0 When a selected edge occurs on the channel input, the current value of the FTM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1.
Page 936 Functional description If the channel input does not have a filter enabled, then the input signal is always delayed 3 rising edges of the system clock, that is, two rising edges to the synchronizer plus one more rising edge to the edge detector. In other words, the CHnF bit is set on the third rising edge of the system clock after a valid edge occurs on the channel input.
Page 937: Output Compare Mode
Chapter 38 FlexTimer Module (FTM) one rising edge to the filter output, plus one more to the edge detector. In other words, CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on the channel input. The clock for the counter in the channel input filter is the system clock divided by 4.
Page 938 Functional description MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow match match overflow overflow previous value channel (n) output previous value CHnF bit TOF bit Figure 38-219. Example of the Output Compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003...
Page 939: Edge-Aligned Pwm (Epwm) Mode
Chapter 38 FlexTimer Module (FTM) 38.4.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 • DECAPEN = 0 • COMBINE = 0 • CPWMS = 0, and • MSnB = 1 The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width (duty cycle) is determined by (CnV −...
Page 940: Center-Aligned Pwm (Cpwm) Mode
Functional description MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output CHnF bit previous value TOF bit Figure 38-223. EPWM signal with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow when the CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV).
Page 941 Chapter 38 FlexTimer Module (FTM) The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the period is determined by 2 × (MOD − CNTIN). See the following figure. MOD must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
Page 942 Functional description counter counter MOD = 0x0008 overflow overflow CnV = 0x0005 channel (n) match in channel (n) match in channel (n) match in down counting down counting up counting channel (n) output previous value CHnF bit TOF bit Figure 38-226. CPWM signal with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up.
Page 943: Combine Mode
Chapter 38 FlexTimer Module (FTM) 38.4.8 Combine mode The Combine mode is selected when: • FTMEN = 1 • QUADEN = 0 • DECAPEN = 0 • COMBINE = 1, and • CPWMS = 0 In Combine mode, an even channel (n) and adjacent odd channel (n+1) are combined to generate a PWM signal in the channel (n) output.
Page 944 Functional description The following figures illustrate the PWM signals generation using Combine mode. FTM counter C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 38-229. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V <...
Page 945 Chapter 38 FlexTimer Module (FTM) FTM counter C(n+1)V C(n)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 38-231. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter MOD = C(n+1)V C(n)V...
Page 946 Functional description FTM counter C(n+1)V CNTIN C(n)V channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-234. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD FTM counter C(n+1)V = C(n)V CNTIN...
Page 947 Chapter 38 FlexTimer Module (FTM) FTM counter C(n)V = C(n+1)V = CNTIN channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-236. Channel (n) output if (C(n)V = C(n+1)V = CNTIN) FTM counter MOD = C(n+1)V =...
Page 948 Functional description FTM counter C(n+1)V CNTIN C(n)V channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-239. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter C(n)V CNTIN...
Page 949 Chapter 38 FlexTimer Module (FTM) FTM counter C(n)V C(n+1)V CNTIN channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-241. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)V C(n)V...
Page 950: Complementary Mode
Functional description FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output not fully 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output not fully 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-243. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 38.4.8.1 Asymmetrical PWM In Combine mode, the control of the PWM signal first edge, when the channel (n) match occurs, that is, FTM counter = C(n)V, is independent of the control of the PWM signal...
Page 951: K22 Sub-Family Reference Manual, Rev. 4, November
Chapter 38 FlexTimer Module (FTM) • CPWMS = 0, and • COMP = 0 channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 38-244.
Page 952 Functional description 38.4.10.2 MOD register update The following table describes when MOD register is updated: Table 38-304. MOD register update When Then MOD register is updated CLKS[1:0] = 0:0 When MOD register is written, independent of FTMEN bit. • CLKS[1:0] ≠ 0:0, and According to the CPWMS bit, that is: •...
Page 953: Pwm Synchronization
Chapter 38 FlexTimer Module (FTM) 38.4.11 PWM synchronization The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV, OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the FTM counter to the CNTIN register value. Note •...
Page 954 Functional description system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Note All hardware trigger inputs have the same behavior. Figure 38-246. Hardware trigger event with HWTRIGMODE = 0 If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it. NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization (SYNCMODE = 1).
Page 955 Chapter 38 FlexTimer Module (FTM) system clock system clock write 1 to SWSYNC bit write 1 to SWSYNC bit SWSYNC bit SWSYNC bit software trigger event software trigger event PWM synchronization PWM synchronization selected loading point Figure 38-247. Software trigger event 38.4.11.3 Boundary cycle and loading points The boundary cycle definition is important for the loading points for the registers MOD, CNTIN, and C(n)V.
Page 956 Functional description loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 38-248.
Page 957 Chapter 38 FlexTimer Module (FTM) begin legacy SYNCMODE PWM synchronization bit ? enhanced PWM synchronization MOD register is MOD register is updated by software trigger updated by hardware trigger SWWRBUF HWWRBUF bit ? bit ? hardware software trigger trigger TRIGn SWSYNC bit ? bit ?
Page 958 Functional description loading point. If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared according to Hardware trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated...
Page 959 Chapter 38 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 38-252. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit...
Page 960 Functional description 38.4.11.5 CNTIN register synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1).
Page 961 Chapter 38 FlexTimer Module (FTM) begin update OUTMASK register at update OUTMASK register by each rising edge of system clock PWM synchronization SYNCHOM bit ? SYNCMODE rising edge no = bit ? of system clock ? legacy = yes PWM synchronization update OUTMASK with its buffer value enhanced PWM synchronization...
Page 962 Functional description If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger.
Page 963 Chapter 38 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 38-258. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used 38.4.11.8 INVCTRL register synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value.
Page 964 Functional description begin update INVCTRL register at update INVCTRL register by each rising edge of system clock PWM synchronization INVC bit ? SYNCMODE bit ? rising edge no = of system clock ? = yes update INVCTRL with its buffer value enhanced PWM synchronization INVCTRL is updated INVCTRL is updated...
Page 965 Chapter 38 FlexTimer Module (FTM) The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits.
Page 966 Functional description 38.4.11.10 FTM counter synchronization The FTM counter synchronization is a mechanism that allows the FTM to restart the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value, except for channels in Output Compare mode, and the FTM counter is forced to its initial counting value defined by CNTIN register.
Page 967 Chapter 38 FlexTimer Module (FTM) begin legacy SYNCMODE PWM synchronization bit ? enhanced PWM synchronization FTM counter is reset by FTM counter is reset by software trigger hardware trigger SWRSTCNT HWRSTCNT bit ? bit ? hardware TRIGn software SWSYNC trigger bit ? trigger bit ?
Page 968 Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 38-263. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1), (PWMSYNC = 0), and software trigger was used system clock write 1 to TRIG0 bit...
Page 969: Inverting
Chapter 38 FlexTimer Module (FTM) 38.4.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when: • FTMEN = 1 • QUADEN = 0 • DECAPEN = 0 • COMBINE = 1 •...
Page 970 Functional description channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting NOTE...
Page 971: Software Output Control
Chapter 38 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting...
Page 972 Functional description Both CHnOC and CHnOCV bits in SWOCTRL register are buffered and updated with their buffer value according to SWOCTRL register synchronization. The following figure shows the channels (n) and (n+1) outputs signals when the software output control is used. In this case the channels (n) and (n+1) are set to Combine and Complementary mode.
Page 973: Deadtime Insertion
Chapter 38 FlexTimer Module (FTM) Table 38-307. Software ouput control behavior when (COMP = 1) CH(n)OC CH(n+1)OC CH(n)OCV CH(n+1)OCV Channel (n) Output Channel (n+1) Output is not modified by SWOC is not modified by SWOC is forced to zero is forced to zero is forced to zero is forced to one is forced to one...
Page 974 Functional description If POL(n) = 1, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n) match (FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, when the channel (n+1) match (FTM counter = C(n+1)V) occurs, the channel (n+1) output remains at the high value until the end of the deadtime delay when the channel (n +1) output is cleared.
Page 975 Chapter 38 FlexTimer Module (FTM) 38.4.14.1 Deadtime insertion corner cases If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value).
Page 976: Output Mask
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 38-272. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle 38.4.15 Output mask...
Page 977: Fault Control
Chapter 38 FlexTimer Module (FTM) the beginning of new PWM cycles FTM counter channel (n) output (before output mask) CHnOM bit channel (n) output (after output mask) channel (n) output is disabled configured PWM signal starts to be available in the channel (n) output Figure 38-273.
Page 978 Functional description is reset and starts counting up. As long as the new state is stable on the fault input n, the counter continues to increment. If the 5-bit counter overflows, that is, the counter exceeds the value of the FFVAL[3:0] bits, the new fault input n value is validated. It is then transmitted as a pulse edge to the edge detector.
Page 979 Chapter 38 FlexTimer Module (FTM) If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred and (FAULTEN = 1), then outputs are forced to their safe values: • Channel (n) output takes the value of POL(n) •...
Page 980: Polarity Control
Functional description 38.4.16.2 Manual fault clearing If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the FAULTF bit is cleared and a new PWM cycle begins. See the following figure. the beginning of new PWM cycles FTM counter channel (n) output...
Page 981: Initialization
Chapter 38 FlexTimer Module (FTM) • If POLn = 0, the channel (n) output polarity is high, so the logical one is the active state and the logical zero is the inactive state. • If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state.
Page 982: Features Priority
Functional description 38.4.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. pair channels (m) - channels (n) and (n+1) FTM counter QUADEN DECAPEN COMBINE(m) CPWMS C(n)V MS(n)B CH(n)OC MS(n)A...
Page 983: Initialization Trigger
Chapter 38 FlexTimer Module (FTM) The channel trigger output provides a trigger signal that is used for on-chip modules. The FTM is able to generate multiple triggers in one PWM period. Because each trigger is generated for a specific channel, several channels are required to implement this functionality.
Page 984 Functional description • When there is a write to CNT register. • When there is the FTM counter synchronization. • If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits. The following figures show these cases. CNTIN = 0x0000 MOD = 0x000F CPWMS = 0...
Page 985: Capture Test Mode
Chapter 38 FlexTimer Module (FTM) CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter CLKS[1:0] bits initialization trigger Figure 38-283. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The initialization trigger output provides a trigger signal that is used for on-chip modules.
Page 986 Functional description FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AD 0x78AE0x78AF 0x78B0 0x78AC write 0x78AC write to CNT CHnF bit 0x0300 0x78AC NOTE - FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and (MOD = 0xFFFF) - FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 38-284.
Page 987: Dual Edge Capture Mode
Chapter 38 FlexTimer Module (FTM) Table 38-312. Clear CHnF bit when DMA = 1 CHnIE How CHnF Bit Can Be Cleared CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and then writing a 0 to CHnF bit.
Page 988 Functional description The C(n)V register stores the value of FTM counter when the selected edge by channel (n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM counter when the selected edge by channel (n+1) is detected at channel (n) input. In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n +1)V registers are read.
Page 989 Chapter 38 FlexTimer Module (FTM) 38.4.24.2 Continuous Capture mode The Continuous Capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 1). In this capture mode, the edges at the channel (n) input are captured continuously. The ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A bits select the final edge to be captured.
Page 990 Functional description FTM counter channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. - Problem 1: channel (n) input = 1, set DECAP, not clear CH(n)F, and clear CH(n+1)F.
Page 991 Chapter 38 FlexTimer Module (FTM) FTM counter channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 38-287.
Page 992 Functional description The following figure shows an example of the Dual Edge Capture – One-Shot mode used to measure the period between two consecutive rising edges. The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next period.
Page 993 Chapter 38 FlexTimer Module (FTM) when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n +1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)V and C(n+1)V registers are ready for reading. FTM counter channel (n) input (after the filter...
Page 994: Quadrature Decoder Mode
Functional description When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)V register when a falling edge occurs in the channel (n) input signal. C(n)V register has the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred.
Page 995 Chapter 38 FlexTimer Module (FTM) PHAFLTREN CH0FVAL[3:0] synchronizer CNTIN phase A input filtered phase A signal PHAPOL PHBPOL Filter FTM counter system clock enable FTM counter up/down direction PHBFLTREN CH1FVAL[3:0] TOFDIR QUADIR synchronizer phase B input filtered phase B signal Filter Filter Figure 38-291.
Page 996 Functional description phase B (counting direction) phase A (counting rate) FTM counter +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 increment/decrement FTM counter CNTIN 0x0000 Time Figure 38-292. Quadrature Decoder – Count and Direction Encoding mode If QUADMODE = 0, then the Phase A and Phase B Encoding mode is enabled;...
Page 997 Chapter 38 FlexTimer Module (FTM) phase A phase B FTM counter +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 increment/decrement FTM counter CNTIN...
Page 998 Functional description phase A phase B FTM counter increment/decrement FTM counter CNTIN 0x0000 Time set TOF set TOF clear TOFDIR clear TOFDIR Figure 38-295. FTM counter overflow in down counting for Quadrature Decoder mode 38.4.25.1 Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications.
Page 999: Bdm Mode
Chapter 38 FlexTimer Module (FTM) phase A phase B FTM counter CNTIN 0x0000 Time Figure 38-297. Motor position jittering near maximum and minimum count value The first highlighted transition causes a jitter on the FTM counter value near the maximum count value (MOD). The second indicated transition occurs on phase A and causes the FTM counter transition between the maximum and minimum count values which are defined by MOD and CNTIN registers.
Page 1000: Intermediate Load
Functional description Table 38-313. FTM behavior when the chip Is in BDM mode (continued) BDMMODE CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers Counter Functional can be set Functional mode Functional mode mode Note that if BDMMODE[1:0] = 2’b00 then the channels outputs remain at the value when the chip enters in BDM mode, because the FTM counter is stopped.