Revision History; Table 148. Error Calculation For Programmed Baud Rates At F; Table 149. Error Calculation For Programmed Baud Rates At F Pclk = 100 Mhz Or F Pclk = 50 Mhz; Table 226. Document Revision History - ST STM32F412 Reference Manual

RM0402
32

Revision history

24-Nov-2015
23-Mar-2016
26-May-2016
10-Jun-2016

Table 226. Document revision history

Date Revision
1 Initial release.
Updated
– Table 1: Register boundary addresses
– Table 24: RCC register map and reset values for
STM32F412xx
– Figure 2: Memory map
– Section 6.3: RCC registers
– Section 9.5.5: DMA stream x configuration register
(DMA_SxCR)
– Section 14.4.4: Serial channel transceivers
2
– Section 30.6.1: MCU device ID code
– Section 30.16.2: Debug support for timers, watchdog,
bxCAN and I
Added:
– Table 148: Error calculation for programmed baud
rates at f
PCLK
oversampling by 16
– Table 149: Error calculation for programmed baud
rates at f
PCLK
oversampling by 8
Updated:
3 – Table 91: DFSDM register map and reset values
– Section 30.6.1: MCU device ID code
Updated:
– Section 6.3.13: RCC APB1 peripheral clock enable
register (RCC_APB1ENR)
– Section 6.3.23: RCC PLLI2S configuration register
(RCC_PLLI2SCFGR)
– Section 6.3.24: RCC Dedicated Clocks Configuration
Register (RCC_DCKCFGR)
– Section 6.3.26: RCC Dedicated Clocks Configuration
4
Register (RCC_DCKCFGR2)
– Section 14: Digital filter for sigma delta modulators
(DFSDM)
– Section 23.4.9: FMPI2C master mode
– Section 23.7.2: Control register 2 (FMPI2C_CR2)
Added:
– Section 6.3.25: RCC clocks gated enable register
(CKGATENR)
RM0402 Rev 6
Revision history
Changes
2
C
= 100 MHz or f = 50 MHz,
PCLK
= 100 MHz or f = 50 MHz,
PCLK
1157/22
1158