ST STM32F412 Reference Manual page 1158

Revision history
26-Oct-2018
30-Oct-2020
1158/22
Table 226. Document revision history (continued)
Date Revision
Updated:
– Section 5.3.4: Batch acquisition mode
– Section 6.3.19: RCC APB2 peripheral clock enabled
in low power mode register (RCC_APB2LPENR)
– Section 6.3.24: RCC Dedicated Clocks Configuration
Register (RCC_DCKCFGR)
– Figure 38: Mode 2 write access waveforms
5
– Section 12.3.2: QUADSPI pins
– Section 15: True random number generator (RNG)
– Table 120: FMPI2C configuration
– Section 29: USB on-the-go full-speed (OTG_FS)
Added:
– Section 14.3: DFSDM implementation
– Table 87: DFSDM break connection
Updated
– Table 5: Flash module organization
6
– Table 23: PWR - register map and reset values
– Section 30.6.1: MCU device ID code
RM0402 Rev 6
Changes
RM0402