Hitachi SH7751 Hardware Manual page 26

Figure 14.15 Dual Address Mode/Burst Mode External Bus


Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)
External Bus..................................................................................................... 509
Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus
(Level Detection) ............................................................................................. 510
Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus
(Level Detection) ............................................................................................. 511
Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus
(Edge Detection) .............................................................................................. 512
Figure 14.20 Single Address Mode/Burst Mode External Bus
(Level Detection) ............................................................................................. 513
Figure 14.21 Single Address Mode/Burst Mode External Bus
(Edge Detection) .............................................................................................. 514
Figure 14.22 Single Address Mode/Burst Mode External Bus
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:
Row Hit Write) ................................................................................................ 515
Figure 14.23 On-Demand Transfer Mode Block Diagram.................................................... 520
Figure 14.24 System Configuration in On-Demand Data Transfer Mode ............................ 522
Figure 14.25 Data Transfer Request Format ......................................................................... 523
Figure 14.26 Single Address Mode/Synchronous DRAM
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS
latency=3, TPC=3)........................................................................................... 526
Figure 14.27 Single Address Mode/External Device
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1,
TRWL=2, TPC=1) ........................................................................................... 527
Figure 14.28 Dual Address Mode/Synchronous DRAM
Figure 14.29 Single Address Mode/Burst Mode/External Bus
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529
Figure 14.30 Single Address Mode/Burst Mode/External Device
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529
Figure 14.31 Single Address Mode/Burst Mode/External Bus
Transfer/Channel 0 On-Demand Data Transfer ............................................... 530
Figure 14.32 Single Address Mode/Burst Mode/External Device
Transfer/Channel 0 On-Demand Data Transfer ............................................... 531
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 532
Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data
Transfer) .......................................................................................................... 533
Figure 14.35 Read from Synchronous DRAM Precharge Bank............................................ 534
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)................ 534
Figure 14.37 Read from Synchronous DRAM (Row Hit)..................................................... 535
Figure 14.38 Write to Synchronous DRAM Precharge Bank ............................................... 535
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) ................... 536
(Edge Detection), DACK (Read Cycle) ............................................... 508

External Bus/

On-Chip SCI

External Bus/

External Bus/

External Bus/

External Bus/

External Bus/

External Device Longword

Synchronous DRAM Longword

SRAM Longword Transfer ...... 528

External Device 32-Byte

External Bus 32-Byte

External Device 32-Bit

External Bus 32-Bit
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