Hitachi SH7751 Hardware Manual page 24

Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle ............................................................................................. 410
Figure 13.35 Auto-Refresh Operation................................................................................... 411
Figure 13.36 Synchronous DRAM Auto-Refresh Timing .................................................... 412
Figure 13.37 Synchronous DRAM Self-Refresh Timing ...................................................... 413
Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 415
Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ............... 416
Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) 417
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM .................................. 418
Figure 13.41 Burst ROM Basic Access Timing .................................................................... 420
Figure 13.42 Burst ROM Wait Access Timing ..................................................................... 421
Figure 13.43 Burst ROM Wait Access Timing ..................................................................... 421
Figure 13.44 Example of PCMCIA Interface........................................................................ 426
Figure 13.45 Basic Timing for PCMCIA Memory Card Interface ....................................... 427
Figure 13.46 Wait Timing for PCMCIA Memory Card Interface......................................... 428
Figure 13.47 PCMCIA Space Allocation.............................................................................. 429
Figure 13.48 Basic Timing for PCMCIA I/O Card Interface................................................ 430
Figure 13.49 Wait Timing for PCMCIA I/O Card Interface ................................................. 431
Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface........................ 432
Figure 13.51 Example of 32-Bit Data Width MPX Connection ........................................... 434
Figure 13.52 MPX Interface Timing 1
(Single Read Cycle, AnW = 0, No External Wait) .......................................... 435
Figure 13.53 MPX Interface Timing 2
(Single Read, AnW = 0, One External Wait Inserted) ..................................... 436
Figure 13.54 MPX Interface Timing 3
(Single Write Cycle, AnW = 0, No External Wait) ......................................... 437
Figure 13.55 MPX Interface Timing 4
(Single Write, AnW = 1, One External Wait Inserted) .................................... 438
Figure 13.56 MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait)............................................ 439
Figure 13.57 MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control)..................................... 440
Figure 13.58 MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait) ........................................... 441
Figure 13.59 MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control).................................... 442
Figure 13.60 MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)............................................................................. 443
Figure 13.61 MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)............................................................................. 444
Rev. 3.0, 04/02, page xxiii of xxxviii