Mc68302 Bus Interface Signal Summary - Motorola MC68302 User Manual

5.10 MC68302 BUS INTERFACE SIGNAL SUMMARY
5-10
Table 5-2 is a summary of all bus signals discussed in the previous para-
graphs. It shows the direction of each pin for the following bus masters:
core, IDMA, and external. Each bus master can access either internal dual-
port RAM and registers, or an external device or memory. When an external
bus master accesses the internal dual-port RAM or registers, the access is
required to be synchronous.
When the internal core is disabled, BR and BG change their direction, and
BCLR becomes bidirectional.
Table 5-2. Bus Signal Summary
Master t
Core or IDMA External Master
Access tot Internal External Internal External
Memory
Memory Memory Memory
Signal Name
Direction Space
Space Space Space
A23-A 1, FC2-FCO
1/0 0 0
I I
AS,UDS 1/0 0 0
I
I
LDS, R/W
RMC
BCLR Open Drain 0 0 0 0
IAC 0
0 0
0 0
D15-DO Read 1/0 0 I 0
I
Write
110
0 0 I I
DTACK
1/0 0
**
0
**
BR
I I
I I I
-
BG
0
0 0 0 0
BGACK 1/0 I-Core I-Core
I I
0-IDMA
0-IDMA
- -
HALT
Open Drain 1/0
1/0 I I
RESET Open Drain 110 1/0 I I
- -
BERR Open Drain
1/0***
110***
1/0*** 1/0***
- -
IPL2-IPLO
I
I I I I
AVEC I I I I I
IOUT2-IOUTO 0 0 0 0 0
**If DTACK is generated automatically (internally) by the chip-select logic, then it is an output.
Otherwise, it is an input.
***BERR is an open-drain output, and may be asserted by the IMP when the hardware watchdog
is used, or when the chip-select logic detects address conflict or write protect violation. BERR
may be asserted by external logic in all cases.
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