System Configuration; Vco/Pll Clock Synthesizer; Chip-Select Logic; External Bus Interface - Motorola DragonBall MC68328 User Manual

Overview
nally generated interrupts and also handles the mask and wake-up selection control for
power control. The low-power logic can control the CPU power dissipation by a frequency
change or stopping it altogether. The SIM28 can also configure the pin to let users select
either dedicated I/O or parallel I/O. This feature helps increase the number of available I/O
ports by reclamation when the dedicated function is not in use.
1.2.2.1 SYSTEM CONFIGURATION. The MC68328 processor system configuration logic
consists of a system control register (SCR) that lets users configure these major function
operations:
• System status and control logic
• Register double mapping
• Bus error generation control
• Module control registers protection from access by user programs
1.2.2.2 VCO/PLL CLOCK SYNTHESIZER. The clock synthesizer can operate with either
an external crystal or an external oscillator for reference, using the internal phase-locked
loop (PLL). The other option is for an external clock to directly drive the clock signal at the
operational frequency.
1.2.2.3 CHIP-SELECT LOGIC. The MC68328 processor provides 16 programmable, gen-
eral-purpose, chip-select signals. For a given chip-select block, users may choose: (1)
whether the chip-select allows read-only or both read and write accesses, (2) whether a
DTACK is automatically generated for this chip-select, and (3) the number of wait states
(from zero to six) until the DTACK will be generated.
1.2.2.4 EXTERNAL BUS INTERFACE. The external bus interface handles the transfer of
information between the internal MC68EC000 core and the memory, peripherals, or other
processing elements in the external address space. It consists of a 16-bit 68000 data bus
interface for internal-only devices and a programmable 8-bit or 16-bit data bus interface to
external devices.
1.2.2.5 INTERRUPT CONTROLLER. The interrupt controller accepts and prioritizes both
internal and external interrupt requests and generates a vector number during the CPU
interrupt-acknowledge cycle. Interrupt nesting is also provided so that an interrupt service
routine of a lower priority interrupt may be suspended by a higher priority interrupt request.
The on-chip interrupt controller has these major features:
• Prioritized interrupt sources (internal and external)
• Fully nested interrupt environment
• Programmable vector generation
• Unique vector number generated for each interrupt level
• Interrupt masking
• Wakeup interrupt masking
1-8 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL MOTOROLA