Memory Read Data Parity Error - Motorola MPC8240 User Manual

Error Reporting
register equals the threshold value in the ECC single-bit error trigger register. A memory
select error occurs when a local memory transaction address falls outside of the physical
memory boundaries as programmed in the memory boundary registers. A refresh overflow
error occurs when no refresh transaction occurs within the equivalent of 16 refresh cycles.
In all cases, if the memory transaction is initiated by a PCI master, ErrDR1[3] is set; if the
memory transaction is initiated by the processor core, ErrDR1[3] is cleared.
ErrDR2[7] is cleared to indicate that the error address in the processor/PCI error address
register is valid. If the ECC single-bit error trigger threshold is reached, then the error
address indicates the address of the most recent ECC single-bit error. Note that when a
parity or ECC error occurs on the last beat of a transaction and another transaction to the
same page has started, the MPC8240 cannot provide the error address and the
corresponding bus status. In these cases, ErrDR2[7] is set to indicate that the error address
in the processor/PCI error address register is not valid. The MPC8240 cannot provide the
error address and the bus status for refresh overflow errors, so ErrDR2[7] is set for these
errors as well.
If the transaction is initiated by the processor core or by a PCI master with bit 6 of the PCI
command register cleared, the error status information is latched, but the transaction
continues and terminates normally.

13.3.2.1 Memory Read Data Parity Error

When MCCR1[PCKEN] is set, the MPC8240 checks memory parity on every memory read
cycle and generates the parity on every memory write cycle that emanates from the
MPC8240. When a read parity error occurs, ErrDR1[2] is set.
The MPC8240 does not check parity for transactions in the local ROM address space. Note
that the processor should not check parity for local ROM space transactions because the
parity data will be incorrect for these accesses.
13.3.2.2 Memory ECC Error
The MPC8240 can be configured to perform an ECC check on every memory read cycle;
it also generates the ECC check data on every memory write cycle. SDRAM systems use
the in-line ECC configuration shown in Table 6-9 on page 6-14; FPM and EDO DRAM
systems use the ECC configuration shown in Table 6-20 on page 6-54.
When a single-bit ECC error occurs, the ECC single-bit error counter register is
incremented by one, and its value is compared to the value in the ECC single-bit error
trigger register. If the values are equal, ErrDR1[2] is set. In addition to single-bit errors, the
MPC8240 detects all 2-bit errors, all errors within a nibble (one-half byte), and any other
multi-bit error that does not alias to either a single-bit error or no error. When a multi-bit
ECC error occurs, ErrDR2[3] is set.
Write parity errors are reported in ErrDR1[2] (memory read parity error/ECC single-bit
error exceeded). Read parity and multiple-bit ECC errors are reported in ErrDR2[3] (ECC
multi-bit error).
13-8 MPC8240 Integrated Processor User's Manual