Integer Unit (Iu); Floating-Point Unit (Fpu); Load/Store Unit (Lsu) - Motorola MPC8240 User Manual

PowerPC Processor Core Features

5.2.4.1 Integer Unit (IU)

The IU executes all integer instructions. The IU executes one integer instruction at a time,
performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER
register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose
registers are provided to support integer operations. Stalls due to contention for GPRs are
minimized by the automatic allocation of rename registers. The processor core writes the
contents of the rename registers to the appropriate GPR when integer instructions are
retired by the completion unit.

5.2.4.2 Floating-Point Unit (FPU)

The FPU contains a single-precision multiply-add array and the floating-point status and
control register (FPSCR). The multiply-add array allows the processor to efficiently
implement multiply and multiply-add operations. The FPU is pipelined so that
single-precision instructions and double-precision instructions can be issued back-to-back.
Thirty-two floating-point registers are provided to support floating-point operations. Stalls
due to contention for FPRs are minimized by the automatic allocation of rename registers.
The processor writes the contents of the rename registers to the appropriate FPR when
floating-point instructions are retired by the completion unit.
The processor supports all IEEE 754 floating-point data types (normalized, denormalized,
NaN, zero, and infinity) in hardware, eliminating the latency incurred by software
exception routines.

5.2.4.3 Load/Store Unit (LSU)

The LSU executes all load and store instructions and provides the data transfer interface
between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective
addresses, performs data alignment, and provides sequencing for load/store string and
multiple instructions.
Load and store instructions are issued and translated in program order; however, the actual
memory accesses can occur out of order. Synchronizing instructions are provided to
enforce strict ordering where needed.
Cacheable loads, when free of data dependencies, execute in an out-of-order manner with
a maximum throughput of one per cycle and a two-cycle total latency. Data returned from
the cache is held in a rename register until the completion logic commits the value to a GPR
or FPR. Store operations do not occur until a predicted branch is resolved. They remain in
the store queue until the completion logic signals that the store operation is definitely to be
completed to memory.
The processor core executes store instructions with a maximum throughput of one per cycle
and a three-cycle total latency. The time required to perform the actual load or store
operation varies depending on whether the operation involves the cache, system memory,
or an I/O device.
Chapter 5. PowerPC Processor Core 5-7