ST STM32L4+ Series Reference Manual page 1957

RM0432
Bit 8 CKEN1: Clock enable of bitstream clock number 1
This bit is set and cleared by software.
0: SAI_CK1 clock disabled
1: SAI_CK1 clock enabled
Note: It is not recommended to configure this bit when PDMEN = 1.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 MICNBR[1:0]: Number of microphones
This bit is set and cleared by software.
00: Configuration with 2 microphones
01: Configuration with 4 microphones
10: Configuration with 6 microphones
11: Configuration with 8 microphones
Note: It is not recommended to configure this field when PDMEN = 1.*
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 PDMEN: PDM enable
This bit is set and cleared by software. This bit allows to control the state of the PDM interface block.
Make sure that the SAI in already operating in TDM master mode before enabling the PDM interface.
0: PDM interface disabled
1: PDM interface enabled
53.6.19 SAI PDM delay register (SAI_PDMDLY)
Address offset: 0x0048
Reset value: 0x0000 0000
31 30 29
Res. DLYM4R[2:0]
rw rw
15 14 13
Res. DLYM2R[2:0]
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 DLYM4R[2:0]: Delay line for second microphone of pair 4
This bit is set and cleared by software.
000: No delay
001: Delay of 1 T
010: Delay of 2 T
...
111: Delay of 7 T
This field can be changed on-the-fly.
Bit 27 Reserved, must be kept at reset value.
28 27 26 25
Res. DLYM4L[2:0]
rw rw rw
12 11 10 9
Res. DLYM2L[2:0]
rw rw rw
period
SAI_CK
periods
SAI_CK
periods
SAI_CK
24 23 22
Res. DLYM3R[2:0]
rw rw
8 7 6
Res. DLYM1R[2:0]
rw rw
RM0432 Rev 6
Serial audio interface (SAI)
21 20 19 18
Res.
rw rw rw
5 4 3 2
Res.
rw rw rw
17 16
DLYM3L[2:0]
rw rw
1 0
DLYM1L[2:0]
rw rw
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