Figure 14.19 Receive Data Sampling Timing In Asynchronous Mode - Renesas H8 Series Hardware Manual

Section 14 Serial Communication Interface 3 (SCI3)
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing

Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode

Rev. 1.00 Aug. 28, 2006 Page 240 of 400
REJ09B0268-0100
16 clocks
8 clocks
0 7
Start bit
15 0 7
D0
15 0
D1