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Figure 19-6 illustrates the horizontal timing of a single horizontal line, which is represented
by five RAM entries:
• A—The section of the line where both blanking and HSYNC are asserted.
• B—The section of the line where HSYNC is negated and blanking is asserted.
• C—The section of the line where both signals are negated while the driven data is
background
• D—The section of the line where both signals are negated while the driven data is the
image data.
• E—The section of the line where blanking is asserted and HSYNC is negated.
A
LINE 3
HSYNC
FIELD
BLANK
118 PIXELS
(236 CLOCKS)
MOTOROLA
B
C
D
LINE 4
720 PIXELS
(1440 CLOCKS)
858 PIXELS
(1716 CLOCKS)
4 PIXELS
(8 CLOCKS)
Figure 19-6. NTSC Horizontal Timing
MPC823e REFERENCE MANUAL
Video Controller
E
16 PIXELS
(32 CLOCKS)
19-21
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