Table of Contents
Advertisement
18.3.9.3 ACTIVE INTERFACE. Active (TFT) interfaces use the following signals. These
signals have a programmable polarity. T
T
is a circuit delay that is specified in Section 22 DC Electrical Characteristics . In
delay
Figure 18-12, the reference to 1-16 lines signifies that the time period depends on how the
the VPW field in the LCVCR register. The reference to 0-1,023 lines signifies that the time
period varies between 0 and 1,023 scan lines (WBF field in the LCVCR).
• SHIFT/CLK—When the LCD output enable signal is valid, data is latched on the
asserted edge of CLK.
• FRAME/VSYNC—This vertical sync signal initiates a new frame.
• LOAD/HSYNC—This horizontal sync signal initiates a new line.
• LCD_AC/LOE—When the LCD output enable signal is valid, it enables data to be
shifted into the display. When it is disabled, the data is invalid and no data is transferred.
• LD—The LCD data bus represents 4-, 8-, or 12-bit data. For monochrome displays,
4- or 8-bit data is the same as passive interfaces and 12-bit data is used for color
displays.
Use the following formulas to calculate the HSYNC and VSYNC cycles using the
user-programmable parameters that are located in the LCD control registers.
VSYNC = (HSYNC × L) +WBF
HSYNC = SHIFT/CLK × (P ÷ LCDBW +12 + TWBL)
SHIFT/CLK = LCDCLK / K
LCDCLK = VCOOUT / LCD_div_factor (programmed)
Where:
L = Number of lines in panel ( ÷ 2 for dual-scan displays and +VPW in LCVCR for active).
WBF = Number of waits between frames.
P = Number of pixels per line in panel ( × 2 for dual-scan displays).
LCDBW = LCD bus width (4- or 8-bit for passive displays and 1 for active).
TWBL = WBL + N = Total number of waits between lines, where:
N = 7 in configurations in which the panel type is a passive monochrome with a 4-bit data bus
configured with two or four bits per pixel. BPIX = 01 or 10, CLOR = 0, TFT =0, and LBW = 0, as defined
in the LCCR.
N = 5 for all other configurations
VCOOUT = SPLL output frequency.
LCD_div_factor = LCD_div_factor is programmed in the SCCR (DFLCD × DFALCD).
K = Inner rate factor that depends on your configuration:
3:
For a 4-bit per pixel color passive display with an 8-bit LCD data bus width
single-scan.
2:
For a 4-bit per pixel color passive display with an 8-bit LCD data bus width
dual-scan or with a 4-bit LCD data bus width single-scan.
1:
For all other configurations.
MOTOROLA
is the cycle time of the LCD clock (SHIFT/CLK).
cyc
MPC823e REFERENCE MANUAL
LCD Controller
18-17
Advertisement
Table of Contents
