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Video Controller
19.3.9 Video Frame Buffer A Start Address Register (Set 1)
The 32-bit video frame buffer A start address register set 1 (VFAA1) holds the start address
of the set_1 odd field. Since all bursts are required to be 16-byte aligned, this register does
not use the four least-significant bits of the address.
VFAA1
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
NOTE: X = - "Don't Care" and — = Undefined.
FAA1—Frame Buffer A Start Address for Set 1
This field designates the start address of the frame buffer A set 0 in system memory.
19-14
3
4
5
6
7
FAA1
—
R/W
(IMMR & 0xFFFF0000) + 0x820
19
20
21
22
23
FAA1
—
R/W
(IMMR & 0xFFFF0000) + 0x822
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
13
14
15
29
30
31
X
—
R/W
MOTOROLA
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