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Video Controller
19.3.7 Video Frame Buffer B Start Address Register (Set 0)
The 32-bit video frame buffer B start address register set 0 (VFBA0) holds the start address
of the set_0 even field. Since all bursts must be 16-byte aligned, this register does not use
the four least-significant bits of the address.
VFBA0
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
NOTE: X = "Don't Care" and — = Undefined.
FBA0—Frame Buffer B Start Address for Set 0
This field designates the start address of the frame buffer B set 0 in system memory.
19-12
3
4
5
6
7
FBA0
—
R/W
(IMMR & 0xFFFF0000) + 0x818
19
20
21
22
23
FBA0
—
R/W
(IMMR & 0xFFFF0000) + 0x81A
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
13
14
15
29
30
31
X
—
R/W
MOTOROLA
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