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19.3.2 Video Status Register
The 8-bit memory-mapped video status register (VSR) is used to report certain events to the
core. When an event is recognized, the video controller sets the corresponding bit in the
video status register, regardless of the corresponding mask bit. The video status register
can be read at any time. A bit is cleared by writing a one (writing a zero has no effect). More
than one bit may be cleared at a time.
VSR
BIT
0
1
FIELD
RESERVED
CAS
RESET
0
0
R/W
R/W
R
ADDR
Bits 0 and 2–4—Reserved
These bits are reserved and must be set to 0.
CAS—Current Active Set
This read-only bit indicates the currently active RAM array and FIFO control register set.
0 = RAM_0 and FIFO register set_0 are currently active.
1 = RAM_1 and FIFO register set_1 are currently active.
BERR—Bus Error
This status bit is set if a read cycle associated with the video controller was terminated by
the assertion of a TEA signal. A maskable interrupt is generated to the core as long as this
bit is set.
UN—Underrun
This bit indicates that a FIFO underrun condition has been detected. An underrun condition
occurs when the video controller FIFO is empty before a frame is completed. If the EIEN bit
is set in the VCCR, then an interrupt is generated to the system interface unit at the level
specified in the IRQL field of VCCR.
EOF—End Of Frame
This status bit is set when a RAM line, with the INT bit set, is executed. If the RAM line is
repeated for more than one clock cycle, EOF will only be set at the last cycle of execution.
This bit is typically used to mark the completion of a frame. If the IEN bit in the VCCR is
enabled, an interrupt is generated to the system interface unit at the level specified in the
IRQL field of VCCR.
MOTOROLA
2
3
4
RESERVED
0
R/W
+ 0x804
(IMMR & 0xFFFF0000)
MPC823e REFERENCE MANUAL
Video Controller
5
6
7
BERR
UN
EOF
0
0
0
R/W
R/W
R/W
19-7
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