Texas Instruments TMS320C6A816 Series Technical Reference Manual page 20

C6-integra dsp+arm processors
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19.3.44 Received Frame Length Low Register (RXFLL)
19.3.45 Received Frame Length High Register (RXFLH)
19.3.46 UART Autobauding Status Register (UASR)
20
Universal Serial Bus (USB)
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20.1
Introduction
20.1.1 Overview
20.1.2 Acronyms, Abbreviations, and Definitions
20.1.3 Features Supported
20.1.4 Features Not Supported
20.1.5 Functional Block Diagram
20.1.6 Supported Use Case(s)
20.1.7 Industry Standard(s) Compliance
20.1.8 Non-Industry Standard(s)
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20.2
Architecture
20.2.1 Clock Control
20.2.2 Signal Descriptions
20.2.3 VBUS Voltage Sourcing Control
20.2.4 Pull-up/Pull-Down Resistors
20.2.5 Role Assuming Method
20.2.6 USB Signal Conditioning
20.2.7 USB PHY Initialization
20.2.8 Indexed and Non-Indexed Register Spaces
20.2.9 Dynamic FIFO Sizing
20.2.10 USB Controller Host and Peripheral Modes Operation
20.3
Protocol Description(s)
20.3.1 USB Controller Peripheral Mode Operation
20.3.2 USB Controller Host Mode Operation
20.4
Communications Port Programming Interface (CPPI) 4.1 DMA
20.4.1 CPPI Terminology
20.4.2 Data Structures
20.4.3 Queue Manager
20.4.4 Memory Regions and Linking RAM
20.4.5 Zero Length Packets
20.4.6 CPPI DMA Scheduler
20.4.7 CPPI DMA State Registers
20.4.8 CPPI DMA Protocols Supported
20.4.9 USB Data Flow Using DMA
20.5
USB 2.0 Test Modes
20.5.1 TEST_SE0_NAK
20.5.2 TEST_J
20.5.3 TEST_K
20.5.4 TEST_PACKET
20.5.5 FIFO_ACCESS
20.5.6 FORCE_HOST
20.6
Reset Considerations
20.6.1 Software Reset Considerations
20.6.2 Hardware Reset Considerations
20.7
Interrupt Support
20.7.1 CPU Interrupts
20.7.2 Interrupt Description
20.7.3 Interrupt Condition Control
20.8
Supported Use Cases
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20.9
Registers
20
Contents
Preliminary
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© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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