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1.13.5 Mailbox Registers
Table 1-101
lists the Mailboxes available in DM816x. The previous register set is applicable to these
mailboxes. See the device-specific data manual for the memory address of these mailboxes.
Mailbox Type
System Mailbox
Table 1-102
lists the memory-mapped registers for the Mailbox Registers. See the device-specific data
manual for the memory address of these registers.
Offset
Acronym
0000h
MAILBOX_REVISION
0010h
MAILBOX_SYSCONFIG Mailbox System Configuration Register
0040h + (4h *
MAILBOX_MESSAGE_
m)
m (1)
0080h + (4h *
MAILBOX_FIFOSTATU
m)
S_m (1)
00C0h + (4h *
MAILBOX_MSGSTATU
m)
S_m (1)
0100h + (10h * MAILBOX_IRQSTATUS
u)
_RAW_u (2)
0104h + (10h * MAILBOX_IRQSTATUS
u)
_CLR_u (2)
0108h + (10h * MAILBOX_IRQENABLE
u)
_SET_u (2)
010Ch + (10h * MAILBOX_IRQENABLE
u)
_CLR_u (2)
0140h
RESERVED
SPRUGX9 – 15 April 2011
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Preliminary
Table 1-101. Mailboxes
User Number(u)
0 to 3
Table 1-102. Mailbox Registers Mapping Summary
Register Description
Mailbox Revision Register
Mailbox Message Register
Mailbox FIFO Status Register
Mailbox Message Status Register
Mailbox IRQ RAW Status Register
Mailbox IRQ Clear Status Register
Mailbox IRQ Enable Set Register
Mailbox IRQ Enable Clear Register
Reserved
© 2011, Texas Instruments Incorporated
Mailbox Number(m)
0 to 11
Mailbox
Messages per Mailbox
4
Section
Section 1.13.5.1
Section 1.13.5.2
Section 1.13.5.3
Section 1.13.5.4
Section 1.13.5.5
Section 1.13.5.6
Section 1.13.5.7
Section 1.13.5.8
Section 1.13.5.9
217
Chip Level Resources
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